公开(公告)号：US20140269010A1

公开(公告)日：2014-09-18

申请号：US13890899

申请日：2013-05-09

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G11C11/4096

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system is provided for transmitting signals. The system includes a ground-referenced single-ended signaling (GRS) driver circuit that is configured to pre-charge a first capacitor to store a first charge between a first output node and a first reference node based on a first input data signal during a first pre-charge phase and drive an output signal relative to a ground network based on the first charge during a first drive phase. A control circuit is configured to generate a first set of control signals based on the first input data signal and a first clock signal, where the first set of control signals causes the first GRS driver circuit to operate in either the first pre-charge phase or in the first drive phase.

Abstract translation: 提供用于发送信号的系统。 该系统包括接地参考单端信令（GRS）驱动器电路，其被配置为在第一输入节点和第一参考节点之间基于第一输入数据信号预先对第一电容器预充电以在第一输出节点和第一参考节点之间存储第一电荷 第一预充电阶段，并且在第一驱动阶段期间基于第一充电来驱动相对于地面网络的输出信号。 控制电路被配置为基于第一输入数据信号和第一时钟信号产生第一组控制信号，其中第一组控制信号使第一GRS驱动电路在第一预充电阶段或第 在第一个驱动阶段。

公开(公告)号：US20140254298A1

公开(公告)日：2014-09-11

申请号：US13794563

申请日：2013-03-11

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40622 ,  G11C11/40626 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016

Abstract: A system and method are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is configured to refresh the first region of a memory at the first refresh rate and refresh the second region of the memory at the second refresh rate.

Abstract translation: 提供了一种用于刷新动态存储器的系统和方法。 以第一刷新率刷新存储器的第一区域，并且以与第一刷新率不同的第二刷新率刷新存储器的第二区域。 存储器控制器被配置为以第一刷新率刷新存储器的第一区域并以第二刷新率刷新存储器的第二区域。

公开(公告)号：US20140240016A1

公开(公告)日：2014-08-28

申请号：US13775063

申请日：2013-02-22

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356121

Abstract: A double-edge-triggered flip-flop circuit and a method for operating the double-edge-trigger flip-flop circuit are provided. Sub-circuits of a flip-flop circuit are coupled to a ground supply and decoupled the sub-circuits from a power supply when a clock signal is asserted. The sub-circuits generate trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated, levels of the second pair of signals are maintained when the clock signal is asserted, and an output signal is transitioned to equal an input signal based on the trigger signals when the clock signal is asserted.

Abstract translation: 提供双边沿触发触发器电路和用于操作双边沿触发器触发器电路的方法。 当时钟信号被断言时，触发器电路的子电路耦合到接地电源并将子电路与电源解耦。 子电路产生包括第一对信号和第二对信号的触发信号。 评估第一对信号，当时钟信号被断言时，第二对信号的电平被维持，并且当时钟信号被断言时，输出信号基于触发信号转换到等于输入信号。

公开(公告)号：US20140232361A1

公开(公告)日：2014-08-21

申请号：US13770975

申请日：2013-02-19

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F1/10 ,  G01R27/14

CPC classification number: G05F1/10 ,  G01R27/14 ,  G06F1/305 ,  H02M3/156 ,  H02M3/1582 ,  H02M2001/0009

Abstract: A system and method are provided for sensing current. A current source is configured to generate a current and a pulsed sense enable signal is generated. A sense voltage across a resistive sense mechanism is sampled according to the sense enable signal, where the sense voltage represents a measurement of the current. A system includes the current source and a current sensing unit. The current source is configured to generate a current. The current sensing unit is coupled the current source and is configured to generate a pulsed sense enable signal and sample the sense voltage across a resistive sense mechanism according to the pulsed sense enable signal.

Abstract translation: 提供了一种感测电流的系统和方法。 电流源被配置为产生电流并且产生脉冲检测使能信号。 根据感测使能信号对电阻感测机构两端的感测电压进行采样，其中感测电压表示电流的测量。 系统包括电流源和电流感测单元。 当前源被配置为生成电流。 电流感测单元耦合电流源，并被配置为产生脉冲感测使能信号，并根据脉冲感测使能信号在电阻感测机构上采样感测电压。

公开(公告)号：US20140210434A1

公开(公告)日：2014-07-31

申请号：US13754791

申请日：2013-01-30

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F1/10

CPC classification number: H02M3/1582 ,  H02M3/155 ,  H02M3/156 ,  H02M3/158 ,  H02M3/1584

Abstract: A system and method are provided for regulating a voltage level at a load. A current source generates a current and a voltage control mechanism provides a portion of the current to regulate the voltage level at the load. When the voltage level at the load is greater than a maximum voltage level, the current source is decoupled from the load and the current source is coupled to a current sink to reduce the voltage level at the load. An electric power conversion comprises the current source and the voltage control mechanism. A downstream controller is configured to control the voltage control mechanism to decouple the current source from the load and couple the current source to a current sink to reduce the voltage level at the load when the voltage level at the load is greater than a maximum voltage level.

Abstract translation: 提供了一种用于调节负载电压电平的系统和方法。 电流源产生电流，并且电压控制机构提供电流的一部分以调节负载处的电压电平。 当负载处的电压电平大于最大电压电平时，电流源与负载分离，并且电流源耦合到电流吸收器以降低负载处的电压电平。 电力转换包括电流源和电压控制机构。 下游控制器被配置为控制电压控制机构以将电流源与负载分离并将电流源耦合到电流吸收器，以在负载处的电压电平大于最大电压电平时降低负载处的电压电平 。

公开(公告)号：US08786345B2

公开(公告)日：2014-07-22

申请号：US13852987

申请日：2013-03-28

Applicant: NVIDIA Corporation

Inventor： Jonah M. Alben ,  William J. Dally

IPC: H03K3/00

CPC classification number: H03K3/286 ,  H03K3/012 ,  H03K3/356139 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract translation: 本发明的一个实施例提出了一种使用完全静态且对制造工艺变化不敏感的单触发低能触发器电路来捕获和存储输入信号电平的技术。单触发低电平触发器电路 能量触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。使用单触发子电路在上升时钟沿设置或复位输出信号Q 。 时钟信号为低电平时，可以设置置位或复位，并在时钟的上升沿触发置位或复位。

公开(公告)号：US08760204B2

公开(公告)日：2014-06-24

申请号：US13681929

申请日：2012-11-20

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Stephen G. Tell

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03K5/135

Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.

Abstract translation: 提供了用于变形容限同步的方法和系统。 接收表示相对于第一时钟信号的第二时钟信号的相位和表示第二时钟信号和第一时钟信号之间的相对周期的周期值的相位值。 基于相位值和周期值计算第二时钟信号相对于与第一时钟信号的下一个转换相对应的第一时钟信号的外推相位值。

公开(公告)号：US20130214839A1

公开(公告)日：2013-08-22

申请号：US13852987

申请日：2013-03-28

Applicant: NVIDIA Corporation

Inventor： Jonah M. Alben ,  William J. Dally

IPC: H03K3/286

CPC classification number: H03K3/286 ,  H03K3/012 ,  H03K3/356139 ,  H03K3/356191

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的单触发低能触发器电路来捕获和存储输入信号电平的技术。 单触发低能触发器电路仅对时钟信号提供三个晶体管栅极负载，并且当输入信号保持不变时，内部节点都不会切换。 输出信号Q在上升时钟沿使用单触发子电路设置或复位。 时钟信号为低电平时，可以设置置位或复位，并在时钟的上升沿触发置位或复位。