Semiconductor storage device
    91.
    发明申请
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号:US20070005876A1

    公开(公告)日:2007-01-04

    申请号:US11440398

    申请日:2006-05-25

    IPC分类号: G06F12/00

    摘要: Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.

    摘要翻译: 在核心单元和接口单元是分离的芯片的半导体存储设备中,数据传输速度增加。 该装置具有通过其中形成有存储单元的多个核芯片,以及形成用于存储单元的外围电路的接口芯片。 多个核芯片通过具有用于临时存储由存储单元输出的数据的锁存电路单元,以及用于临时存储要输入到存储单元的数据的锁存电路单元,并且这些锁存电路单元通过和锁存 电路单元通过级联连接到接口芯片。 由于串联连接的多个锁存电路单元能够进行流水线运行,因此能够实现高速数据传送。

    Class AB CMOS output circuit equiped with CMOS circuit operating by predetermined operating current
    92.
    发明申请
    Class AB CMOS output circuit equiped with CMOS circuit operating by predetermined operating current 失效
    AB类CMOS输出电路配备CMOS电路,通过预定的工作电流工作

    公开(公告)号:US20060114061A1

    公开(公告)日:2006-06-01

    申请号:US11287469

    申请日:2005-11-28

    IPC分类号: H03F3/18

    摘要: In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current Io, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current Io, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.

    摘要翻译: 在具有CMOS电路的AB类CMOS输出电路中,包括第一P和N沟道晶体管并通过预定的工作电流I O 2进行操作,复制电路形成在CMOS电路的半导体衬底上, 并且包括具有与第一P沟道晶体管相同或相似的尺寸的第二P沟道晶体管,以及具有与第一N沟道晶体管的尺寸相等或相似的尺寸的第二N沟道晶体管。 偏置电压电源允许第二P沟道晶体管和N沟道晶体管基于对应于工作电流I 的参考电流Iref工作,将施加到第二P沟道晶体管的第一偏置电压施加到 第一P沟道晶体管,并将施加到第二N沟道晶体管的第二偏置电压施加到第一N沟道晶体管。

    Link state routing techniques
    93.
    发明授权

    公开(公告)号:US07047316B2

    公开(公告)日:2006-05-16

    申请号:US09814854

    申请日:2001-03-23

    IPC分类号: G06F15/13

    摘要: A link state routing communication device allowing path precalculation satisfying the required quality of a connection and reducing the call blocking probability is disclosed. A path satisfying a connection request can be selected from a plurality of precalculated paths which are stored for each destination in a memory. The precalculated paths reflect the latest link resource information using the feasibility check operation or precalculated path update operation. Therefore, a blocking probability of connection setup using precalculated paths can be decreased. In a border node, summarized information is calculated based on precalculated paths and therefore high-speed summarized information calculation is allowed, resulting in reduced computation load.

    Analog to digital converter circuit of successive approximation type operating at low voltage
    94.
    发明申请
    Analog to digital converter circuit of successive approximation type operating at low voltage 失效
    在低电压下工作的逐次逼近型模数转换器电路

    公开(公告)号:US20050200510A1

    公开(公告)日:2005-09-15

    申请号:US11029492

    申请日:2005-01-06

    摘要: In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

    摘要翻译: 在采样和保持中,控制逻辑电路将DA转换器的每个电容器的另一端连接到地电位,并且将来自开关放大器的采样输入模拟信号输出到保持电容器的一端以保持。 在逐次逼近中,它控制开关放大器将其输出端子设置为高阻抗状态,并且保持电容器将其一端连接到地电位。 然后,基于由逐次逼近寄存器保持的数字值将每个电容器的另一端从地电位切换到电源电压,以将输出电压从保持电容器的另一端输出到比较器,并将其进行比较 来自其另一端的输出电压具有中间参考电压,以从逐次逼近寄存器获得数字值。

    Topology aggregation using parameter obtained by internodal negotiation
    95.
    发明授权
    Topology aggregation using parameter obtained by internodal negotiation 失效
    通过国际协商获得的参数的拓扑聚合

    公开(公告)号:US06385201B1

    公开(公告)日:2002-05-07

    申请号:US09069121

    申请日:1998-04-29

    申请人: Atsushi Iwata

    发明人: Atsushi Iwata

    IPC分类号: H04L1228

    摘要: In a hierarchical network, an aggregation parameter is exchanged between a node and its neighbor to agree on a negotiated parameter. A set of physical links between them are aggregated into a logical link according to the negotiated parameter and resource data of the logical link is stored in a database of each node. The resource data is then exchanged between them and the contents of the database of each node are updated with resource data of its neighbor. To optimize the link aggregation, an operating performance of the logical link is evaluated by the node using traffic data from the network, and the negotiated parameter is updated according to the detected operating performance. The updated aggregation parameter of the node is exchanged with its neighbor to agree on a negotiated updated parameter which is used to aggregate the physical links into the logical link.

    摘要翻译: 在分层网络中,聚合参数在节点与其邻居之间交换以协商协商参数。 它们之间的一组物理链路根据协商的参数聚合成逻辑链路,逻辑链路的资源数据存储在每个节点的数据库中。 然后在它们之间交换资源数据,并且利用其邻居的资源数据更新每个节点的数据库的内容。 为了优化链路聚合,节点使用来自网络的流量数据来评估逻辑链路的运行性能,并根据检测到的运行性能更新协商参数。 节点的更新的聚合参数与其邻居交换,以协商用于将物理链路聚合到逻辑链路中的协商更新参数。

    Fault recovery system and transmission path autonomic switching system
    96.
    发明授权
    Fault recovery system and transmission path autonomic switching system 失效
    故障恢复系统和传输路径自主切换系统

    公开(公告)号:US6122753A

    公开(公告)日:2000-09-19

    申请号:US056866

    申请日:1998-04-08

    IPC分类号: H04L1/22 H04L12/56 H04Q11/04

    摘要: Setting of a bypass path upon occurrence of transmission failure, is applicable for large scale network. A system includes signaling means which makes judgment whether bypassing process is performed by an own node by a bypassing process judgement means when a release message issued upon occurrence of failure, is received. Upon judgment to perform bypassing process, computation of bypass path is requested by the path computing means. On the basis of result of computation, bypass path is established and switched. In the bypassing process judgment means, judgment is made whether bypassing process is performed by the signaling means or not depending upon the relationship of positions of the faulty portion and the own node.

    摘要翻译: 发生传输故障时设置旁路路径,适用于大规模网络。 系统包括当接收到发生故障时发布的释放消息时,通过旁路处理判断装置判断是否由自身节点执行旁路处理的信令装置。 在判断为执行旁路过程时,由路径计算装置请求旁路路径的计算。 在计算结果的基础上,建立和切换旁路路径。 在旁路处理判定单元中,根据故障部分与自身节点的位置的关系判断是否由信令装置进行旁路处理。

    Failure restoration system suitable for a large-scale network
    97.
    发明授权
    Failure restoration system suitable for a large-scale network 失效
    故障恢复系统适用于大型网络

    公开(公告)号:US6026077A

    公开(公告)日:2000-02-15

    申请号:US967045

    申请日:1997-11-10

    申请人: Atsushi Iwata

    发明人: Atsushi Iwata

    摘要: In a failure restoration system comprising a distributed hierarchical routing section which is adapted to set up a main path and previously determine an alternate path for the main path in a network, an alternate path selection section is adapted to obtain complete source route information for the main path when it attempts to set up the main path. The alternate path selection section adds the complete source information to a SETUP signaling message for setting up the alternate path, thereby provides a physical alternate path as much different as possible from the main path.

    摘要翻译: 在包括分布式分层路由部分的故障恢复系统中,其适于建立主路径并且预先确定网络中的主路径的替代路径,替代路径选择部分适于获得主主路径的完整源路由信息 尝试设置主路径时的路径。 替代路径选择部分将完整的源信息添加到用于设置备用路径的SETUP信令消息,从而提供与主路径尽可能不同的物理备用路径。

    Address resolution system
    98.
    发明授权
    Address resolution system 失效
    地址解析系统

    公开(公告)号:US5909446A

    公开(公告)日:1999-06-01

    申请号:US907831

    申请日:1997-08-14

    摘要: In an NHRP (NBMA Next Hop Resolution Protocol) address resolution system for transforming a network layer address to a data link layer address in an NBMA (Non-Broadcast, Multi-Access) network not sharing media, an NHRP processing section provides a function of resolving an address while an ATMARP (Asynchronous Transfer Mode Address Resolution Protocol) processing section provides a function of resolving an address on the basis of the ATMARP. A holding section is selectively accessed by the NHRP processing section or ATMARP processing section for holding address information registered by the NHRP or address information registered by the ATMARP. When the NHRP processing section receives an NHRP resolution request packet requesting for a resolution of the address of a given ATMARP terminal's address, the processing section sends, if the ATMARP terminal and a terminal sent the NHRP resolution request packet do not belong to the same subnetwork, a reply representative of the address information of an interface received the request packet.

    摘要翻译: 在用于将网络层地址变换为不共享媒体的NBMA(非广播,多址)网络中的数据链路层地址的NHRP(NBMA下一跳解决协议)地址解析系统中,NHRP处理部分提供 当ATMARP(异步传输模式地址解析协议)处理部分提供基于ATMARP解析地址的功能时,解析地址。 由NHRP处理部分或ATMARP处理部分选择性地访问保持部分,用于保存由NHRP登记的地址信息或由ATMARP登记的地址信息。 当NHRP处理部分接收到要求分配给定ATMARP终端地址的地址的NHRP解析请求分组时,如果ATMARP终端和发送的NHRP解析请求分组的终端不属于同一个子网络,则处理部分发送 接收到接收到请求分组的接口的地址信息的回复代表。

    Digital frequency divider suitable for a frequency synthesizer
    99.
    发明授权
    Digital frequency divider suitable for a frequency synthesizer 失效
    数字分频器适用于频率合成器

    公开(公告)号:US4633194A

    公开(公告)日:1986-12-30

    申请号:US277396

    申请日:1981-06-25

    CPC分类号: H03K23/667 H03L7/193

    摘要: The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.

    摘要翻译: 分频器包括响应于第一控制信号在第一和第二分频因子之间进行选择的第一或预分频计数器,然后响应于第一控制信号对输入信号频率进行分频。 第二和可编程计数器频率将第一或预分频计数器的输出除以第三分频因子。 第三和可编程计数器频率将第一计数器的输出除以小于第三分频因子的第四分频因子。 开关控制电路然后转换第三计数器的输出,并将转换的信号作为第一控制信号提供给第一计数器。 数字分频器适用于锁相环频率合成器的一部分。

    Address arithmetic circuit of a memory unit utilized in a processing
system of digitalized analogue signals
    100.
    发明授权
    Address arithmetic circuit of a memory unit utilized in a processing system of digitalized analogue signals 失效
    在数字化模拟信号的处理系统中使用的存储器单元的地址运算电路

    公开(公告)号:US4594687A

    公开(公告)日:1986-06-10

    申请号:US517348

    申请日:1983-07-26

    CPC分类号: G11C8/04

    摘要: A signal address arithmetic circuit is used for performing address arithmetic required for executing such analog signal algorithms as adaptive predicative coding, adaptive bit allocation in predictive coding, adaptive transform coding, etc. The address arithmetic circuit is constructed of two counters, three registers, two selectors, a shift circuit an adder and AND gate circuits. The first selector selects either one of the first counter, the second counter or a first register, and its output is applied to one input terminal of the adder. The second selector selects either one of the second counter or the third register and its output is directly applied to the other input of the adder. The output of the adder and the content of the second register for each bit are applied to the AND gate circuits and its output is set in the third register, the content thereof being used for memory addressing. According to the type of processing algorithms and corresponding addressing modes, the arithmetic circuit performs the resetting or incrementing of the two counters, controlling the selection operation of the two selection circuits, controlling the number of shifts of the shift circuit, and resetting the third register.

    摘要翻译: 信号地址运算电路用于执行执行自适应预测编码,预测编码中的自适应位分配,自适应变换编码等模拟信号算法所需的地址运算。地址运算电路由两个计数器,三个寄存器,二个 选择器,移位电路,加法器和与门电路。 第一选择器选择第一计数器,第二计数器或第一寄存器中的任一个,并且其输出被加到加法器的一个输入端。 第二选择器选择第二计数器或第三寄存器中的任一个,并且其输出被直接施加到加法器的另一个输入。 加法器的输出和每个位的第二寄存器的内容被加到与门电路,其输出被设置在第三寄存器中,其内容用于存储器寻址。 根据处理算法的类型和相应的寻址模式,算术电路执行两个计数器的复位或递增,控制两个选择电路的选择操作,控制移位电路的移位数,以及复位第三寄存器 。