摘要:
Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.
摘要:
In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current Io, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current Io, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.
摘要翻译:在具有CMOS电路的AB类CMOS输出电路中,包括第一P和N沟道晶体管并通过预定的工作电流I O 2进行操作,复制电路形成在CMOS电路的半导体衬底上, 并且包括具有与第一P沟道晶体管相同或相似的尺寸的第二P沟道晶体管,以及具有与第一N沟道晶体管的尺寸相等或相似的尺寸的第二N沟道晶体管。 偏置电压电源允许第二P沟道晶体管和N沟道晶体管基于对应于工作电流I 的参考电流Iref工作,将施加到第二P沟道晶体管的第一偏置电压施加到 第一P沟道晶体管,并将施加到第二N沟道晶体管的第二偏置电压施加到第一N沟道晶体管。
摘要:
A link state routing communication device allowing path precalculation satisfying the required quality of a connection and reducing the call blocking probability is disclosed. A path satisfying a connection request can be selected from a plurality of precalculated paths which are stored for each destination in a memory. The precalculated paths reflect the latest link resource information using the feasibility check operation or precalculated path update operation. Therefore, a blocking probability of connection setup using precalculated paths can be decreased. In a border node, summarized information is calculated based on precalculated paths and therefore high-speed summarized information calculation is allowed, resulting in reduced computation load.
摘要:
In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.
摘要:
In a hierarchical network, an aggregation parameter is exchanged between a node and its neighbor to agree on a negotiated parameter. A set of physical links between them are aggregated into a logical link according to the negotiated parameter and resource data of the logical link is stored in a database of each node. The resource data is then exchanged between them and the contents of the database of each node are updated with resource data of its neighbor. To optimize the link aggregation, an operating performance of the logical link is evaluated by the node using traffic data from the network, and the negotiated parameter is updated according to the detected operating performance. The updated aggregation parameter of the node is exchanged with its neighbor to agree on a negotiated updated parameter which is used to aggregate the physical links into the logical link.
摘要:
Setting of a bypass path upon occurrence of transmission failure, is applicable for large scale network. A system includes signaling means which makes judgment whether bypassing process is performed by an own node by a bypassing process judgement means when a release message issued upon occurrence of failure, is received. Upon judgment to perform bypassing process, computation of bypass path is requested by the path computing means. On the basis of result of computation, bypass path is established and switched. In the bypassing process judgment means, judgment is made whether bypassing process is performed by the signaling means or not depending upon the relationship of positions of the faulty portion and the own node.
摘要:
In a failure restoration system comprising a distributed hierarchical routing section which is adapted to set up a main path and previously determine an alternate path for the main path in a network, an alternate path selection section is adapted to obtain complete source route information for the main path when it attempts to set up the main path. The alternate path selection section adds the complete source information to a SETUP signaling message for setting up the alternate path, thereby provides a physical alternate path as much different as possible from the main path.
摘要:
In an NHRP (NBMA Next Hop Resolution Protocol) address resolution system for transforming a network layer address to a data link layer address in an NBMA (Non-Broadcast, Multi-Access) network not sharing media, an NHRP processing section provides a function of resolving an address while an ATMARP (Asynchronous Transfer Mode Address Resolution Protocol) processing section provides a function of resolving an address on the basis of the ATMARP. A holding section is selectively accessed by the NHRP processing section or ATMARP processing section for holding address information registered by the NHRP or address information registered by the ATMARP. When the NHRP processing section receives an NHRP resolution request packet requesting for a resolution of the address of a given ATMARP terminal's address, the processing section sends, if the ATMARP terminal and a terminal sent the NHRP resolution request packet do not belong to the same subnetwork, a reply representative of the address information of an interface received the request packet.
摘要:
The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.
摘要:
A signal address arithmetic circuit is used for performing address arithmetic required for executing such analog signal algorithms as adaptive predicative coding, adaptive bit allocation in predictive coding, adaptive transform coding, etc. The address arithmetic circuit is constructed of two counters, three registers, two selectors, a shift circuit an adder and AND gate circuits. The first selector selects either one of the first counter, the second counter or a first register, and its output is applied to one input terminal of the adder. The second selector selects either one of the second counter or the third register and its output is directly applied to the other input of the adder. The output of the adder and the content of the second register for each bit are applied to the AND gate circuits and its output is set in the third register, the content thereof being used for memory addressing. According to the type of processing algorithms and corresponding addressing modes, the arithmetic circuit performs the resetting or incrementing of the two counters, controlling the selection operation of the two selection circuits, controlling the number of shifts of the shift circuit, and resetting the third register.