公开(公告)号：US07533213B2

公开(公告)日：2009-05-12

申请号：US12070272

申请日：2008-02-15

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3485 ,  G06F11/349 ,  G06F13/1694 ,  G06F2201/88 ,  G06F2201/885

摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.

摘要翻译： 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括跟踪一个或多个系统度量的至少一个性能计数器，例如页面命中率，预取命中的数量或百分比，高速缓存命中率或百分比，读取速率，读取请求数，写入速率，写入速率， 写请求，速率或百分比的内存总线利用率，本地集线器请求速率或数量，和/或远程集线器请求速率或数量。

公开(公告)号：US07529896B2

公开(公告)日：2009-05-05

申请号：US11433201

申请日：2006-05-11

申请人： Joseph M. Jeddeloh ,  Terry R. Lee

发明人： Joseph M. Jeddeloh ,  Terry R. Lee

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

摘要翻译： 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括存储写入请求的已发布的写入缓冲器，以便随后发出的读取请求可以首先耦合到存储器件。 写请求地址也被发布在缓冲区中，并与随后的读请求地址进行比较。 在正面比较的情况下，指示读请求被引导到较早写请求所针对的地址，从缓冲器提供读数据。 当存储器件不忙于读取请求时，写入请求可以从发布的写入缓冲区传送到存储器件。 写入请求也可以被累积在发布的写入缓冲器中，直到预定数量的写入请求已经被累积或写入请求已经被发布了预定的持续时间。

公开(公告)号：US07521948B2

公开(公告)日：2009-04-21

申请号：US11784346

申请日：2007-04-06

申请人： Joseph M. Jeddeloh ,  Robert Totorica

发明人： Joseph M. Jeddeloh ,  Robert Totorica

IPC分类号： G01R31/02

CPC分类号： G01R31/31905 ,  G01R31/31924 ,  G11C29/56 ,  G11C2029/5602

摘要： An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated test circuit also receives response signals from the integrated circuit sockets indicative of the manner in which integrated circuits in the sockets responded to the test signals. Several of the load boards may be placed on a test head that may be coupled to a host. The integrated test circuit may also be used with an integrated circuit probe card, where the test signals are applied to an integrated circuit coupled to the probe card.

摘要翻译： 集成电路负载板包括其上安装有多个集成电路插座和集成测试电路的基板。 集成测试电路产生应用于集成电路插座的测试信号。 集成测试电路还接收来自集成电路插座的响应信号，指示插座中的集成电路响应于测试信号的方式。 几个负载板可以放置在可以耦合到主机的测试头上。 集成测试电路还可以与集成电路探针卡一起使用，其中测试信号被施加到耦合到探针卡的集成电路。

公开(公告)号：US20090013143A1

公开(公告)日：2009-01-08

申请号：US12233492

申请日：2008-09-18

申请人： Joseph M. Jeddeloh ,  Paul LaBerge

发明人： Joseph M. Jeddeloh ,  Paul LaBerge

IPC分类号： G06F13/00

CPC分类号： G06F1/12 ,  G06F13/1689

摘要： A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

摘要翻译： 存储器模块包括耦合到存储器集线器的若干存储器件。 存储器集线器包括耦合到相应处理器的几个链路接口，耦合到相应存储器设备的多个存储器控制器，将任何链接接口耦合到任何存储器控制器的交叉条交换器，每个存储器设备的写入缓冲器和读取高速缓存，以及 一个读同步模块。 读取同步模块包括写入指针，读取指针和缓冲器。 响应于读取数据的接收，写入指针递增。 响应于来自存储器集线器的读取数据的耦合，读取指针增加。 比较器比较读指针和写指针，比较用来调整存储器的时序。

公开(公告)号：US20080301533A1

公开(公告)日：2008-12-04

申请号：US11639950

申请日：2006-12-15

申请人： Terry R. Lee ,  Joseph M. Jeddeloh

发明人： Terry R. Lee ,  Joseph M. Jeddeloh

IPC分类号： H03M13/00

CPC分类号： H04B10/2504 ,  H04L1/0001 ,  H04L1/242 ,  H04L7/043

摘要： A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

摘要翻译： 一种动态调整通信网络链路控制参数的方法和系统。 通信网络包括通过第一数据链路耦合到接收机的发射机。 发射器和接收器各自具有影响该部件的操作的至少一个相关联的链接控制参数。 根据一种方法，通过第一数据链路传输数据信号，并且捕获发送的数据信号。 将捕获的数据信号的值与这些信号的期望值进行比较，并且调整链路控制参数的值以成功捕获所发送的数字信号。

公开(公告)号：US20080294856A1

公开(公告)日：2008-11-27

申请号：US12169493

申请日：2008-07-08

申请人： Joseph M. Jeddeloh ,  Ralph James

发明人： Joseph M. Jeddeloh ,  Ralph James

IPC分类号： G06F12/00

CPC分类号： G06F13/1642 ,  G06F13/1605 ,  G06F13/1684

摘要： A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

摘要翻译： 一种用于在插入在发送存储器集线器和接收存储器集线器之间的存储器集线器的数据路径上发送读取响应的存储集线器和方法。 在存储器集线器处接收包括指示相关联的读取响应的数据路径配置的数据的仲裁分组。 仲裁分组被解码，并且根据仲裁分组的数据来配置数据路径。 在存储器集线器处接收相关联的读取响应，并且将相关联的读取响应耦合到所配置的数据路径，以将其发送到接收存储器集线器。

公开(公告)号：US07415567B2

公开(公告)日：2008-08-19

申请号：US11398018

申请日：2006-04-04

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F12/00

CPC分类号： G06F13/1642 ,  G06F13/161 ,  G06F13/1684

摘要： A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. The memory hub includes a sequencer and a bypass circuit. When the memory hub is busy servicing one or more memory requests, the sequencer generates and couples the memory requests to the memory devices. When the memory hub is not busy servicing multiple memory requests, the bypass circuit generates and couples a portion of each the memory requests to the memory devices and the sequencer generates and couples the remaining portion of each of the memory requests to the memory devices.

摘要翻译： 一种用于使用存储器集线器从多个存储器件访问数据的计算机系统和方法。 计算机系统包括耦合到存储器集线器控制器的多个存储器模块。 每个存储器模块包括存储器集线器和多个存储器件。 存储器集线器包括定序器和旁路电路。 当存储器集线器正忙于服务一个或多个存储器请求时，定序器生成并将存储器请求耦合到存储器件。 当存储器集线器不忙于服务多个存储器请求时，旁路电路产生并将每个存储器请求的一部分耦合到存储器件，并且定序器产生并将每个存储器请求的剩余部分耦合到存储器件。

公开(公告)号：US07412566B2

公开(公告)日：2008-08-12

申请号：US11510150

申请日：2006-08-24

申请人： Terry R. Lee ,  Joseph M. Jeddeloh

发明人： Terry R. Lee ,  Joseph M. Jeddeloh

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026

摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

摘要翻译： 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括历史逻辑，其基于读取存储器请求来预测存储器件中的哪些地址可能随后从其读取数据。 历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。 响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。 标签逻辑存储与预取数据的地址对应的预取地址。 标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。 如果是，则从预取缓冲器读取所请求的数据。 否则，从存储器件读取所请求的数据。

公开(公告)号：US20080140904A1

公开(公告)日：2008-06-12

申请号：US12070272

申请日：2008-02-15

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/161 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3485 ,  G06F11/349 ,  G06F13/1694 ,  G06F2201/88 ,  G06F2201/885

摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.

摘要翻译： 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括跟踪一个或多个系统度量的至少一个性能计数器，例如页面命中率，预取命中的数量或百分比，高速缓存命中率或百分比，读取速率，读取请求数，写入速率，写入速率， 写请求，速率或百分比的内存总线利用率，本地集线器请求速率或数量，和/或远程集线器请求速率或数量。

公开(公告)号：US07386649B2

公开(公告)日：2008-06-10

申请号：US11544352

申请日：2006-10-05

申请人： Joseph M. Jeddeloh

发明人： Joseph M. Jeddeloh

IPC分类号： G06F13/00 ,  G06F12/08

CPC分类号： G11C5/00 ,  G06F12/0862 ,  G06F13/4022

摘要： A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

摘要翻译： 基于处理器的电子系统包括布置在第一和第二等级中的几个存储器模块。 第一级的存储器模块由几个处理器中的任何一个直接访问，并且第二级的存储器模块由处理器通过第一级的存储器模块访问。 通过改变用于访问第二组中的存储器模块的第一级中的存储器模块的数量来改变处理器和第二级中的存储器模块之间的数据带宽。 每个存储器模块包括耦合到存储器集线器的多个存储器件。 存储器集线器包括耦合到每个存储器设备的存储器控​​制器，耦合到相应处理器或存储器模块的链路接口以及将任何存储器控制器耦合到任何链路接口的交叉开关。