公开(公告)号：US08084308B2

公开(公告)日：2011-12-27

申请号：US12470128

申请日：2009-05-21

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/148 ,  H01L27/105

CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract translation: 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。

公开(公告)号：US08077439B2

公开(公告)日：2011-12-13

申请号：US12265601

申请日：2008-11-05

Applicant: Hooman Darabi ,  Ming Wang Sze ,  Kent Oertle ,  Paul Chang

Inventor： Hooman Darabi ,  Ming Wang Sze ,  Kent Oertle ,  Paul Chang

IPC: H02H9/00

CPC classification number: H01L23/60 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/85444 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.

Abstract translation: 提供了一种降低片上系统中静电放电风险的方法和系统。 在这方面，对于包括在IC内彼此电隔离的多个部分的IC，ESD电流可以经由与IC结合的封装内和/或上的一个或多个路径布线。 一个或多个路径可以电耦合IC的两个或多个部分。 一个或多个路径在集成电路中使用的一个或多个频率处的DC处可具有低阻抗和高阻抗。 IC的一部分可以是用于RF电路的接地平面。 IC的部分之一可以是用于数字电路的接地平面。 一个或多个路径可以在所述包装的一个或多个金属层中制造。

公开(公告)号：US20110232425A1

公开(公告)日：2011-09-29

申请号：US12731360

申请日：2010-03-25

Applicant: Maan-Jyi Chang ,  Paul Chang

Inventor： Maan-Jyi Chang ,  Paul Chang

IPC: B25B13/46 ,  B25B15/04 ,  B25B23/16

CPC classification number: B25B15/04 ,  B25G1/063 ,  B25G1/085

Abstract: A folding tool includes two support plates, a ratchet driver pivotally mounted between the two support plates, a rotation seat rotatably mounted between the two support plates, and a plurality of tips each removably mounted on the rotation seat and each detachably mounted on the ratchet driver. The ratchet driver drives each of the tips to rotate in the operation direction only and idles in the opposite direction so that each of the tips can rotate the screw member in the operation direction successively so as to screw or unscrew the screw member easily and quickly. Thus, when the folding tool is used in a smaller space, each of the tips is driven by the ratchet driver to rotate the screw member in the operation direction successively and to screw or unscrew the screw member easily and quickly.

Abstract translation: 折叠工具包括两个支撑板，一个可枢转地安装在两个支撑板之间的棘轮驱动器，可旋转地安装在两个支撑板之间的旋转座，以及可移除地安装在旋转座上并且可拆卸地安装在棘轮驱动器上的多个尖端 。 棘轮驱动器驱动每个尖端仅在操作方向上旋转并且在相反方向上空转，使得每个尖端可以连续地沿着操作方向旋转螺钉构件，以便容易且快速地拧紧或拧下螺钉构件。 因此，当折叠工具在更小的空间中使用时，每个尖端由棘轮驱动器驱动，以使螺杆构件沿操作方向依次旋转，并且容易且快速地拧紧或拧下螺钉构件。

公开(公告)号：US20110223729A1

公开(公告)日：2011-09-15

申请号：US13108630

申请日：2011-05-16

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y.W. Hsueh ,  Vladmir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y.W. Hsueh ,  Vladmir Rodov

IPC: H01L21/8234

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07964933B2

公开(公告)日：2011-06-21

申请号：US11821234

申请日：2007-06-22

Applicant: Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

Inventor： Paul Chang ,  Geeng-Chuan Chern ,  Prognyan Ghosh ,  Wayne Y. W. Hsueh ,  Vladimir Rodov

IPC: H01L21/76

CPC classification number: H01L27/0629 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/861

Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.

Abstract translation: 一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管 半导体衬底。 介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。 功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

公开(公告)号：US07893492B2

公开(公告)日：2011-02-22

申请号：US12371943

申请日：2009-02-17

Applicant: Stephen W. Bedell ,  Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

Inventor： Stephen W. Bedell ,  Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: H01L21/02

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  Y10S977/72 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.

Abstract translation: 提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。 每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。 包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

公开(公告)号：US20110031473A1

公开(公告)日：2011-02-10

申请号：US12536741

申请日：2009-08-06

Applicant: Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

Inventor： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

IPC: H01L27/11 ,  H01L29/66 ,  H01L21/8239

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  Y10S977/938

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract translation: 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

公开(公告)号：US20090262475A1

公开(公告)日：2009-10-22

申请号：US12265601

申请日：2008-11-05

Applicant: Hooman Darabi ,  Ming Wang Sze ,  Kent Oertle ,  Paul Chang

Inventor： Hooman Darabi ,  Ming Wang Sze ,  Kent Oertle ,  Paul Chang

IPC: H02H9/04

CPC classification number: H01L23/60 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/85444 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.

Abstract translation: 提供了一种降低片上系统中静电放电风险的方法和系统。 在这方面，对于包括在IC内彼此电隔离的多个部分的IC，ESD电流可以经由与IC结合的封装内和/或上的一个或多个路径布线。 一个或多个路径可以电耦合IC的两个或多个部分。 一个或多个路径在集成电路中使用的一个或多个频率处的DC处可具有低阻抗和高阻抗。 IC的一部分可以是用于RF电路的接地平面。 IC的部分之一可以是用于数字电路的接地平面。 一个或多个路径可以在所述包装的一个或多个金属层中制造。

公开(公告)号：US20070159638A1

公开(公告)日：2007-07-12

申请号：US11615986

申请日：2006-12-24

Applicant: Ke-Cai Zeng ,  Paul Chang ,  Jurgen Brendel

Inventor： Ke-Cai Zeng ,  Paul Chang ,  Jurgen Brendel

IPC: G01B9/02

CPC classification number: G01J3/26 ,  G01J3/02 ,  G01J3/0286 ,  G01J3/28 ,  G01J2003/2866 ,  G01M11/331 ,  G01M11/336 ,  G01M11/338 ,  H04B10/07951

Abstract: An optical signal measurement system provides a tunable optical filter. An unknown optical signal is scanned through the tunable optical filter. The wavelength and chromatic dispersion values of the unknown optical signal scanned through the tunable optical filter are measured by operating the tunable optical filter in a scanning mode for at least one of OSA and PMD measurements, and in a stepping mode for CD measurements. The wavelength and the dispersion values in the unknown optical signal are specified.

Abstract translation: 光信号测量系统提供可调光滤波器。 通过可调光滤波器扫描未知的光信号。 通过可调谐滤光器扫描的未知光信号的波长和色散值通过以扫描模式对OSA和PMD测量中的至少一个进行操作，并以用于CD测量的步进模式来测量。 指定未知光信号中的波长和色散值。

公开(公告)号：US20060138132A1

公开(公告)日：2006-06-29

申请号：US11022690

申请日：2004-12-28

Applicant: Chao-Yeh Wu ,  Paul Chang

Inventor： Chao-Yeh Wu ,  Paul Chang

IPC: B65D6/16

CPC classification number: B65D19/0002 ,  B65D11/1873 ,  B65D2519/00024 ,  B65D2519/00059 ,  B65D2519/00184 ,  B65D2519/00218 ,  B65D2519/00233 ,  B65D2519/00273 ,  B65D2519/00298 ,  B65D2519/00353 ,  B65D2519/00502 ,  B65D2519/00512 ,  B65D2519/00611 ,  B65D2519/00661 ,  B65D2519/00711 ,  B65D2519/0086 ,  B65D2519/00995

Abstract: A packing box with cardboard walls includes a pallet base, four wall assemblies, a top cover, a plurality of fasteners and five cardboard pieces. A horizontally extending female edge is provided on each of the four sides of the pallet base. The right and left sides of each wall assembly are provided with a male edge and a female edge to allow two neighboring wall assemblies to engage with each other. The upper and lower sides of each wall assembly are provided with a male edge, and the male edge on the lower side of each wall assembly may rest on and engage with the corresponding female edge of the pallet base. Each side of the top cover has a downwards extending wall edge and a horizontally extending top cover edge so that the top cover may rest on the four wall assemblies via the four top cover edges and the male edges and that the four wall edges may engage with the inner members of the four male edges of the wall assemblies. The cross section of the fasteners has a “” shape, and a fastening groove is provided on each of the fasteners. A threaded hole extends through one arm of the fastener and a bolt may be fitted into the hole. A convex tip is provided on the front tip of the bolt and two protrusions are provided on the other arm of the fastener. Last, the five cardboard pieces are fitted onto the four wall assemblies and the top cover.

Abstract translation: 具有纸板墙的包装盒包括托盘底座，四个壁组件，顶盖，多个紧固件和五个纸板件。 在托盘底座的四个侧面上设有水平延伸的阴边缘。 每个壁组件的右侧和左侧设置有阳边缘和阴边缘，以允许两个相邻的壁组件彼此接合。 每个壁组件的上侧和下侧设置有阳边缘，并且每个壁组件的下侧上的阳边缘可以搁置在托盘底座的相应的凹形边缘上并与其接合。 顶盖的每一侧具有向下延伸的壁边缘和水平延伸的顶盖边缘，使得顶盖可以经由四个顶盖边缘和阳边缘搁置在四个壁组件上，并且四个壁边缘可以与 壁组件的四个公边缘的内部构件。 紧固件的横截面具有““形状，并且在每个紧固件上设置有紧固槽。 螺纹孔延伸穿过紧固件的一个臂，并且螺栓可以装配到孔中。 在螺栓的前端设置有凸起的尖端，并且在紧固件的另一个臂上设置两个突起。 最后，五块纸板装在四个墙组件和顶盖上。