公开(公告)号：US11336251B2

公开(公告)日：2022-05-17

申请号：US16986595

申请日：2020-08-06

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H03H7/01 ,  H03H3/08 ,  H03H7/46 ,  H01F3/00 ,  H01L23/64 ,  H01L23/66 ,  H01L23/538

Abstract: Disclosed are devices and methods for fabricating devices. A device can include a passive portion having at least one metal insulator metal (MIM) capacitor and at least one 2-dimensional (2D) inductor. The device further includes a substrate and the passive portion is formed on the substrate. A magnetic core is embedded in the substrate. A 3-dimensional (3D) inductor is also included having windings formed at least in part in the substrate and at least a portion of the windings being formed around the magnetic core.

公开(公告)号：US11296670B2

公开(公告)日：2022-04-05

申请号：US16750625

申请日：2020-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

IPC: H03H7/38 ,  H04B1/40 ,  H01Q1/22 ,  H01Q1/52

Abstract: Impedance matching transceivers may include a tuning circuit to match the transceiver module impedance to the housing conditions. In some examples, the impedance matching is controlled by tuning-circuits that may be integrated into a transceiver module by using a fan-out package (FO PKG). One example of a tuning circuit may include a switch to isolate the parallel capacitors, such that when the switch is on or closed the parallel capacitors are active.

公开(公告)号：US20220084947A1

公开(公告)日：2022-03-17

申请号：US17024214

申请日：2020-09-17

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Aniket Patil

IPC: H01L23/538

Abstract: An integrated circuit (IC) with reconstituted die interposer for improved connectivity has at least one device or component mounted on an exterior upper surface that couples to a die in an interposer layer within the package. The interposer layer may have interconnect structures, where a first interconnect structure has vias of a first pitch and a second interconnect structure has vias of a second pitch greater than the first pitch. In this manner, the interposer layer acts as a device that can allow conductive coupling for other devices with those pitches to support interconnections between those devices and other devices within the interposer layer.

公开(公告)号：US11152272B2

公开(公告)日：2021-10-19

申请号：US16682554

申请日：2019-11-13

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H01L23/15 ,  H01L21/02 ,  H01L21/8238

Abstract: Certain aspects provide a three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. For example, certain aspects provide a semiconductor device that generally includes one or more first integrated circuits (ICs), a first plurality of pads coupled to components of the one or more first ICs, one or more second ICs, forming glass (FG) material disposed adjacent to the one or more second ICs, and a second plurality of pads, wherein at least one of the second plurality of pads is coupled to components of the one or more second ICs, and wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads.

公开(公告)号：US10433425B1

公开(公告)日：2019-10-01

申请号：US16051876

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Changhan Hobie Yun ,  Jonghae Kim ,  Mario Francisco Velez

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/46 ,  H05K3/40 ,  H05K3/28 ,  H05K1/02

Abstract: A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.

公开(公告)号：US10361149B2

公开(公告)日：2019-07-23

申请号：US15233906

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  David Francis Berdy ,  Daeik Daniel Kim ,  Jonghae Kim

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/14 ,  H01L23/00 ,  H05K1/02 ,  H01L23/64 ,  H05K3/34

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

公开(公告)号：US10332911B2

公开(公告)日：2019-06-25

申请号：US15380800

申请日：2016-12-15

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L21/84 ,  H01L23/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/498 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US10332671B2

公开(公告)日：2019-06-25

申请号：US15345312

申请日：2016-11-07

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Changhan Hobie Yun ,  Daeik Daniel Kim ,  David Francis Berdy ,  Jonghae Kim ,  Yunfei Ma ,  Chengjie Zuo

IPC: H04B5/00 ,  H01F27/02 ,  H01F27/28 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01F27/29 ,  H01F41/06 ,  H01F38/14 ,  H01L23/522 ,  H01L23/64 ,  H01L25/16 ,  H01L49/02

Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

公开(公告)号：US10283257B2

公开(公告)日：2019-05-07

申请号：US14991803

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC: H01F27/28 ,  H01F17/00 ,  H01F41/04 ,  H04B1/40 ,  H01L23/522 ,  H01L27/02 ,  H01L49/02

Abstract: A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.

公开(公告)号：US10171112B2

公开(公告)日：2019-01-01

申请号：US15080472

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Berdy ,  Daeik Kim ,  Changhan Yun ,  Je-Hsiung Lan ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Robert Mikulka ,  Jonghae Kim

IPC: H01P5/18 ,  H04B1/00 ,  H04B1/04 ,  H04B1/3827 ,  H04B1/40 ,  H04L5/14 ,  H03H7/09 ,  H03H7/46 ,  H01P5/02

Abstract: An RF diplexer is provided that includes a first channel and a second channel. The first channel includes a first primary inductor. Similarly, the second channel includes a second primary inductor. A first directional coupler for the first channel includes a first transformer formed by the first primary inductor and also a first secondary inductor. A first terminal for the first secondary inductor is a coupled port for the first directional coupler. A second directional coupler for the second channel includes a second transformer formed by the second primary inductor and also a second secondary inductor. A first terminal for the second secondary inductor is a coupled port for the second directional coupler.