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91.发明授权公开(公告)号：US07305645B1
公开(公告)日：2007-12-04
申请号：US10935488
申请日：2004-09-07
CPC分类号： G06F17/5077 , G06F2217/12 , Y02P90/265
摘要： The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a partially created routing pattern, and a comparing component makes a comparison between the at least partially created routing pattern with one or more patterns in a library of patterns. Routing is controlled based at least in part upon the comparison.
摘要翻译： 本发明涉及一种便于控制集成电路中的平面图上的块的路由的系统和/或方法。 模式收集器接收部分创建的路由模式，并且比较组件在至少部分创建的路由模式与模式库中的一个或多个模式之间进行比较。 至少部分地基于比较来控制路由。
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公开(公告)号：US07251033B1
公开(公告)日：2007-07-31
申请号：US10858757
申请日：2004-06-02
IPC分类号： G01N21/00
CPC分类号： G01N21/94 , G01N2021/95676 , G03F1/84 , G03F7/70916
摘要： A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.
摘要翻译： 提供了一种系统和方法来现场检测标线上的污染物或缺陷。 该系统和方法提供一种系统，其通过掩模版上的清晰区域测量光学透射，并确定掩模版的光学传输是否已被污染物或其他缺陷降解。
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93.发明授权公开(公告)号：US07084988B1
公开(公告)日：2006-08-01
申请号：US09893803
申请日：2001-06-28
IPC分类号： G01B11/24
CPC分类号： H01L22/26
摘要： A system and method for monitoring the creation of semiconductor features with multi-slope profiles by employing scatterometry is provided. The system includes a wafer partitioned into one or more portions and one or more light sources, each light source directing light to one or more devices etched on a wafer, the devices having multi-sloped profiles. Reflected light is collected and converted into data by a measuring system. The data is indicative of the etching at the one or more portions of the wafer. The measuring system provides the data to a process analyzer that determines whether adjustments to etching components are necessary by comparing the data to stored etch parameter values. The system also includes etching components. At least one etch component corresponds to a portion of the wafer and performs the etching thereof. The process analyzer selectively controls the etch components to promote consistent etching of multi-slope profiles/features to compensate for wafer to wafer variations.
摘要翻译： 提供了一种通过采用散射法来监测具有多斜率分布的半导体特征的创建的系统和方法。 该系统包括分为一个或多个部分和一个或多个光源的晶片，每个光源将光引导到在晶片上蚀刻的一个或多个器件，该器件具有多倾斜轮廓。 反射光被测量系统收集并转换成数据。 数据表示在晶片的一个或多个部分处的蚀刻。 测量系统将数据提供给过程分析仪，通过将数据与存储的蚀刻参数值进行比较来确定是否需要对蚀刻部件进行调整。 该系统还包括蚀刻部件。 至少一个蚀刻部件对应于晶片的一部分并执行其蚀刻。 过程分析器选择性地控制蚀刻部件以促进多斜率分布/特征的一致蚀刻以补偿晶片到晶片的变化。
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94.发明授权Use of scatterometry as a control tool in the manufacture of extreme UV masks 失效使用散射测量作为制造极端紫外线掩模的控制工具公开(公告)号：US06879406B1
公开(公告)日：2005-04-12
申请号：US10677041
申请日：2003-10-01
摘要： One aspect of the present invention relates to a system and method for controlling an EUV mask fabrication process using a scatterometer. The system includes an EUV mask fabrication system comprising a translucent substrate having one or more layers of reflective material formed thereon and a patterned photoresist layer as the uppermost layer, a mask inspection system operatively connected to the mask fabrication system for examining the layers as they are being etched and developed by the mask fabrication system and generating data related thereto, and an EUV mask fabrication control system coupled to the mask inspection system for receiving data from the inspection system in order to regulate the mask fabrication system to facilitate obtaining desired critical dimensions. The method involves monitoring the etching of the features, generating data related to the features, and relaying the data to a control system to optimize the EUV mask fabrication process.
摘要翻译： 本发明的一个方面涉及使用散射仪控制EUV掩模制造工艺的系统和方法。 该系统包括EUV掩模制造系统，该系统包括其上形成有一层或多层反射材料的半透明基材和作为最上层的图案化光致抗蚀剂层，与该掩模制造系统可操作地连接的掩模检查系统，以便像它们一样检查这些层 由掩模制造系统蚀刻和显影并产生与之相关的数据，以及耦合到掩模检查系统的EUV掩模制造控制系统，用于从检查系统接收数据，以便调节掩模制造系统以便于获得期望的临界尺寸。 该方法包括监测特征的蚀刻，产生与特征有关的数据，以及将数据中继到控制系统以优化EUV掩模制造工艺。
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95.发明授权公开(公告)号：US06869888B1
公开(公告)日：2005-03-22
申请号：US09901704
申请日：2001-07-11
IPC分类号： H01L21/027 , H01L21/3105 , H01L21/312 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02134 , H01L21/0276 , H01L21/31058 , H01L21/312 , H01L21/76825
摘要： A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.
摘要翻译： 对半导体装置的形成方法进行说明。 该方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 BARC层暴露于电子束（电子束），使得BARC层在至少一个孔中达到流动温度。 执行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的BARC层在蚀刻期间用作耐蚀刻层。
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公开(公告)号：US06845345B1
公开(公告)日：2005-01-18
申请号：US09777435
申请日：2001-02-06
IPC分类号： G06F11/00
CPC分类号： G05B23/0283
摘要： A system for analyzing diagnostic information associated with a spin track is provided. The system includes one or more analysis systems that collect diagnostic information from one or more spin tracks. The system further includes one or more maintenance systems that schedule routine and/or special maintenance based on analysis of the diagnostic information. An alternative aspect of the system further includes one or more control information systems that generate of feedback control information employed in adapting the processes performed by the spin track.
摘要翻译： 提供了一种用于分析与自旋轨迹相关联的诊断信息的系统。 该系统包括从一个或多个自旋轨道收集诊断信息的一个或多个分析系统。 该系统还包括一个或多个维护系统，其基于对诊断信息的分析来调度例行和/或特殊维护。 该系统的另一方面还包括一个或多个控制信息系统，其产生用于适应由旋转轨迹执行的处理的反馈控制信息。
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97.发明授权公开(公告)号：US06813574B1
公开(公告)日：2004-11-02
申请号：US09992599
申请日：2001-11-06
IPC分类号： G01N2186
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Patterned layers in an integrated circuit (IC) or other device are aligned in conjunction with the detection of the topology of the layers. The topology can be used to determine the location of a metrology mark and/or to compensate for a horizontal shift in the apparent location of the metrology mark. Precise detection of topography can be achieved without physical contact with the IC or other device with an atomic force microscope.
摘要翻译： 集成电路（IC）或其他设备中的图案层与层的拓扑结构的检测结合对齐。 拓扑结构可用于确定计量标记的位置和/或补偿计量标记的表观位置的水平位移。 无需使用原子力显微镜与IC或其他器件物理接触即可实现精确的形貌检测。
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98.发明授权System and method for developer endpoint detection by reflectometry or scatterometry 有权用于通过反射测量或散点测量进行开发人员端点检测的系统和方法公开(公告)号：US06758612B1
公开(公告)日：2004-07-06
申请号：US10050471
申请日：2002-01-16
IPC分类号： G03D500
CPC分类号： G03F7/3028
摘要： A system for regulating (e.g., terminating) a development process is provided. The system includes one or more light sources, each light source directing light to one or more patterns and/or gratings on a wafer. Light reflected from the patterns and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides development related data to a processor that determines the acceptability of the development of the respective portions of the wafer. The collected light may be analyzed by scatterometry and/or reflectometry systems to produce development related data and the development related data may be examined to determine whether a development process end point has been reached, at which time the system can control the development process and terminate development.
摘要翻译： 提供了一种用于调节（例如，终止）显影过程的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个图案和/或光栅。 从图案和/或光栅反射的光被测量系统收集，该系统处理所收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 该测量系统将开发相关数据提供给处理器，该处理器确定晶片各个部分的可接受性。 所收集的光可以通过散射法和/或反射测量系统进行分析以产生开发相关数据，并且可以检查开发相关数据以确定是否已经达到开发过程终点，此时系统可以控制开发过程并终止 发展。
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99.发明授权Monitoring of concentration of nitrogen in nitrided gate oxides, and gate oxide interfaces 失效监测氮化栅氧化物和栅极氧化物界面的氮浓度公开(公告)号：US06721046B1
公开(公告)日：2004-04-13
申请号：US09903885
申请日：2001-07-12
IPC分类号： G01B1100
CPC分类号： H01L21/28185 , G01N21/4788 , G01N21/55 , G01N21/8422 , G01N2021/4126 , G01N2021/4735 , G01N2021/8416 , H01L21/28202 , H01L22/26 , H01L29/518
摘要： A system for regulating nitrided gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more nitrided gate oxide layers being deposited and/or formed on a wafer. Light reflected from the nitrided gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The measuring system provides nitrogen concentration related data to a processor that determines the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The system also includes one or more nitrided gate oxide layer formers where a nitride gate oxide former corresponds to a respective portion of the wafer and provides for nitrided gate oxide layer formation thereon. The processor selectively controls the nitrided gate oxide layer formers to regulate nitrided gate oxide layer formation on the respective nitrided gate oxide layer formations on the wafer, and particularly to control, in situ, the amount of nitrogen incorporated into the gate oxide layer.
摘要翻译： 提供了一种用于调节氮化栅氧化层形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氮化栅极氧化物层。 从氮化栅氧化层反射的光被测量系统收集，该系统处理所收集的光。 所收集的光表示晶片上相应的氮化栅极氧化物层的氮浓度。 测量系统向处理器提供氮浓度相关数据，该处理器确定晶片上相应的氮化栅极氧化物层的氮浓度。 该系统还包括一个或多个氮化栅极氧化物层形成器，其中氮化物栅极氧化物形成体对应于晶片的相应部分并且在其上形成氮化的栅极氧化物层。 处理器选择性地控制氮化栅极氧化物层形成器来调节晶片上相应的氮化栅极氧化物层形成物上的氮化栅极氧化物层形成，并且特别地原位控制掺入到栅极氧化物层中的氮的量。
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100.发明授权System and method for in situ control of post exposure bake time and temperature 失效曝晒后烘烤时间和温度的现场控制系统和方法公开(公告)号：US06641963B1
公开(公告)日：2003-11-04
申请号：US09845239
申请日：2001-04-30
IPC分类号： G03F900
摘要： A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof. The processor selectively controls the temperature controlling devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译： 提供了一种用于调节后曝光烘烤处理温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上被烘烤和硬化的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的烘烤和硬化。 测量系统向处理器提供烘烤和硬化相关数据，该处理器确定晶片的相应部分的烘烤和硬化。 该系统还包括多个温度控制装置，每个这样的装置对应于晶片的相应部分并提供其加热和/或冷却。 处理器选择性地控制温度控制装置，以调节晶片各部分的温度。
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