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128 条记录 (耗时 0.031 秒)

    Voltage generating circuit and method
    91.
    发明授权
    Voltage generating circuit and method 有权
    电压发生电路及方法

    公开(公告)号：US06850110B2

    公开(公告)日：2005-02-01

    申请号：US10108276

    申请日：2002-03-27

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G06F7/64

    CPC分类号： H02M3/073 ,  H02M2003/075

    摘要： A voltage generating circuit and method thereof for preventing a current from flowing from a voltage generating node to a pumping node in transiting of the circuit from an active operation to a pre-charge operation are provided. The voltage generating circuit comprises a pre-charge circuit for pre-charging a pumping node and a voltage transmitting control node during a pre-charge operation; a voltage pumping circuit for pumping a signal at the pumping node during an active operation; a voltage transmitting circuit for transmitting the signal from the pumping node to a voltage generating node in response to a signal at the voltage transmitting control node during the active operation; and a countercurrent preventing circuit for varying the signal at the voltage transmitting control node based on the signal at the pumping node during the pre-charge operation and for preventing a current from flowing between the pumping node and the voltage transmitting control node during the active operation.

    摘要翻译： 提供一种电压产生电路及其方法，用于防止电流从电压产生节点流向泵送节点，以将电路从有源操作转移到预充电操作。 电压产生电路包括用于在预充电操作期间预充电泵浦节点和电压发送控制节点的预充电电路; 用于在主动操作期间泵送泵送节点处的信号的电压泵浦电路; 电压发送电路，用于在主动操作期间响应于电压发送控制节点处的信号将信号从泵送节点发送到电压产生节点; 以及逆流防止电路，用于在预充电操作期间基于泵送节点处的信号来改变电压发送控制节点处的信号，并且用于在主动操作期间防止在泵送节点和电压发送控制节点之间流动的电流 。

    Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
    93.
    发明申请
    Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion 有权
    方法和存储器系统具有双数据选通模式和单反数据选通模式之间的模式选择

    公开(公告)号：US20050005053A1

    公开(公告)日：2005-01-06

    申请号：US10733413

    申请日：2003-12-12

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401

    CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C7/1075

    摘要： A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

    摘要翻译： 存储器系统和将数据读取和写入到存储器件的方法选择性地在具有数据反转的单个DQS模式中操作，并且以双DQS模式操作。 该装置和方法采用数据选通模式改变装置，用于在第一数据选通模式和第二数据选通模式之间选择性地改变存储装置的操作。

    Voltage and time control circuits
    94.
    发明授权
    Voltage and time control circuits 有权
    电压和时间控制电路

    公开(公告)号：US06788132B2

    公开(公告)日：2004-09-07

    申请号：US10147553

    申请日：2002-05-17

    申请人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

    发明人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

    IPC分类号： G05F302

    CPC分类号： G05F1/465

    摘要： Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

    摘要翻译： 提供了集成电路，其包括电压控制电路，其被配置为将预定电路电压规范之外的电路电压调整到预定电路电压规范内，使得集成电路器件不再有缺陷。 还提供了集成电路，其包括信号时间延迟控制电路，其被配置为将预定电路延迟时间规范之外的电路延迟时间调整到预定电路延迟时间规范内，使得集成电路装置不再有缺陷。 还提供了相应的操作方法。

    Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell
    97.
    发明授权
    Bitline sense amplifier, memory core including the same and method of sensing charge from a memory cell 有权
    位线读出放大器，包括相同的存储器核心以及从存储器单元感测电荷的方法

    公开(公告)号：US08432762B2

    公开(公告)日：2013-04-30

    申请号：US13006832

    申请日：2011-01-14

    申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    IPC分类号： G11C7/02

    CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

    摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

    摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。

    Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
    100.
    发明授权
    Latency control circuit and method thereof and an auto-precharge control circuit and method thereof 失效
    延迟控制电路及其方法和自动预充电控制电路及其方法

    公开(公告)号：US07911862B2

    公开(公告)日：2011-03-22

    申请号：US12585428

    申请日：2009-09-15

    申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

    发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

    摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

    摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。