公开(公告)号：US07583484B2

公开(公告)日：2009-09-01

申请号：US10644718

申请日：2003-08-20

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H02H3/22

CPC分类号： H01L27/0285

摘要： A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.

摘要翻译： 用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。 传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。 该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

公开(公告)号：US07485905B2

公开(公告)日：2009-02-03

申请号：US11459650

申请日：2006-07-25

申请人： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

发明人： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

IPC分类号： H01L29/80 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/7835

摘要： An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

摘要翻译： 一种静电放电保护装置，包括多指门，具有第二导电性的第一轻掺杂区，第二导电性的第一重掺杂区和第二导电性的第二轻掺杂区。 多指门包括在第一导电性的有源区域上并联连接的多个指状物。 第二导电性的第一轻掺杂区域设置在半导体衬底中并且在两个指状物之间。 第二导电性的第一重掺杂区域设置在第二导电性的第一轻掺杂区域中。 第二导电性的第二轻掺杂区域位于第二导电性的第一轻掺杂区域的下方并与其邻接。

公开(公告)号：US20090008710A1

公开(公告)日：2009-01-08

申请号：US11773364

申请日：2007-07-03

申请人： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

发明人： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878

摘要： A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

摘要翻译： 半导体器件包括在半导体衬底上的栅电极，其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域，其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度，并且其中第二宽度基本上小于第一宽度。

公开(公告)号：US07420252B2

公开(公告)日：2008-09-02

申请号：US11337147

申请日：2006-01-20

申请人： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

发明人： Kuo-Ming Wu ,  Jian-Hsing Lee ,  Yi-Chun Lin ,  Chi-Chih Chen

IPC分类号： H01L23/62

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/4238

摘要： A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.

摘要翻译： 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域，其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上，所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构，用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200％ 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电（ESD）电流的阻抗。

公开(公告)号：US20080173945A1

公开(公告)日：2008-07-24

申请号：US11655896

申请日：2007-01-22

申请人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee ,  Shih-Hsorng Shen ,  Yu-Ting Lin ,  Yun-Sheng Huang

发明人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee ,  Shih-Hsorng Shen ,  Yu-Ting Lin ,  Yun-Sheng Huang

IPC分类号： H01L23/60 ,  H01L21/00

CPC分类号： H01L23/60 ,  H01L23/585 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

摘要翻译： 提供了形成在用于在集成电路中消散静电放电和/或累积电荷的半导体衬底中的半导体器件。 在一个实施例中，该器件包括半导体衬底; 形成在衬底上的多层金属线; 多个通孔插塞穿过所述金属线层之间的金属间电介质层，并且其中所述通孔插塞互连金属线; 以及形成在所述多个金属线层上的虚拟焊盘，所述虚设焊盘具有连接到其上的二极管并接地以提供用于静电放电和/或累积电荷的放电路径。

公开(公告)号：US20070241406A1

公开(公告)日：2007-10-18

申请号：US11402907

申请日：2006-04-13

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Juing-Yi Wu ,  Chong-Gim Gan ,  Dun-Nian Yaung

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Juing-Yi Wu ,  Chong-Gim Gan ,  Dun-Nian Yaung

IPC分类号： H01L23/62

CPC分类号： H01L29/0847 ,  H01L23/60 ,  H01L27/0277 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit has functional circuitry coupled to a terminal. An electrostatic discharge protector can be coupled to the terminal to protect the functional circuitry from an electrostatic discharge. A substrate includes a first semiconductor material with a first dopant type. A plurality of drain segments adjoin the substrate. Each of the drain segments has a first conductor, a second conductor, and a third conductor. A central via set in a central region of the drain segment couples the second conductor to the third conductor. A peripheral via set in a peripheral region of the drain segment couples the first conductor to the second conductor. A plurality of source segments adjoin the substrate and laterally interlace with the drain segments. If an electrostatic discharge is detected at the terminal of the integrated circuit, an electrical current of the ESD is directed into the electrostatic discharge protector and distributed substantially uniformly among a plurality of resistive paths in the electrostatic discharge protector.

摘要翻译： 集成电路具有耦合到终端的功能电路。 静电放电保护器可以耦合到端子以保护功能电路免受静电放电。 衬底包括具有第一掺杂剂类型的第一半导体材料。 多个漏极段邻接衬底。 每个漏极段具有第一导体，第二导​​体和第三导体。 设置在排水段的中心区域的中心通孔将第二导体连接到第三导体。 设置在漏极段的外围区域中的周边通孔将第一导体耦合到第二导体。 多个源区段与衬底相邻并与排水段横向交错。 如果在集成电路的端子处检测到静电放电，则ESD的电流被引导到静电放电保护器中并且基本均匀地分布在静电放电保护器中的多个电阻路径之中。

公开(公告)号：US20060289935A1

公开(公告)日：2006-12-28

申请号：US11512850

申请日：2006-08-29

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  C.S Tang

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： A layout structure for an ESD protection circuit includes a first MOS device area having a first and second doped regions of the same polarity disposed at two sides of a first conductive gate layer, and a third doped region disposed along the first doped region at one side of the first conductive gate layer. The third doped region has a polarity different from that of the first and second doped regions, such that the third doped region and the second doped region form a diode for enhancing dissipation of ESD current during a negative ESD event.

摘要翻译： ESD保护电路的布局结构包括：第一MOS器件区域，具有设置在第一导电栅极层的两侧的具有相同极性的第一和第二掺杂区域;以及第三掺杂区域，沿第一掺杂区域设置在一侧 的第一导电栅极层。 第三掺杂区域具有与第一和第二掺杂区域不同的极性，使得第三掺杂区域和第二掺杂区域形成用于在负ESD事件期间增强ESD电流的耗散的二极管。

公开(公告)号：US20060215337A1

公开(公告)日：2006-09-28

申请号：US11134539

申请日：2005-05-19

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H02H9/00

CPC分类号： H01L27/0262

摘要： An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

公开(公告)号：US07081662B1

公开(公告)日：2006-07-25

申请号：US11199833

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/00 ,  H01L29/73

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US20050213274A1

公开(公告)日：2005-09-29

申请号：US10812378

申请日：2004-03-29

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262

摘要： An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer, and a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground, wherein a voltage drop across the diode string increases the SCR gate holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.

摘要翻译： 公开了具有改进的ESD保护的输入和输出（I / O）电路。 电路具有输出缓冲器，其具有耦合到PMOS晶体管的NMOS晶体管，ESD保护电路具有集成在其中并耦合到输出缓冲器的寄生可控硅整流器（SCR），以及二极管串，其具有预定数量的二极管 NMOS晶体管的源节点并接地，其中二极管串上的电压降增加了SCR栅极保持电压，从而为ESD保护电路设置ESD保护保持电压。