公开(公告)号：US11600313B2

公开(公告)日：2023-03-07

申请号：US17518446

申请日：2021-11-03

Applicant: Tohoku University

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

公开(公告)号：US11563169B2

公开(公告)日：2023-01-24

申请号：US15776902

申请日：2016-11-18

Applicant: TOHOKU UNIVERSITY

Inventor： Hideo Sato ,  Yoshihisa Horikawa ,  Shunsuke Fukami ,  Shoji Ikeda ,  Fumihiro Matsukura ,  Hideo Ohno ,  Tetsuo Endoh ,  Hiroaki Honjo

IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

Abstract: A magnetic tunnel junction element (10) includes a configuration in which a reference layer (14) that includes a ferromagnetic material, a barrier layer (15) that includes O, a recording layer (16) that includes a ferromagnetic material including Co or Fe, a first protective layer (17) that includes O, and a second protective layer (18) that includes at least one of Pt, Ru, Co, Fe, CoB, FeB, or CoFeB are layered.

公开(公告)号：US11557719B2

公开(公告)日：2023-01-17

申请号：US16967364

申请日：2019-01-30

Applicant: TOHOKU UNIVERSITY

Inventor： Shunsuke Fukami ,  Aleksandr Kurenkov ,  William Andrew Borders ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/00 ,  H01L43/04 ,  G06N3/063 ,  G11C11/16 ,  G11C11/18 ,  G11C11/54 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10

Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to the reference layer.

公开(公告)号：US11514964B2

公开(公告)日：2022-11-29

申请号：US16770411

申请日：2018-12-10

Applicant: TOHOKU UNIVERSITY

Inventor： Hiroki Koike ,  Tetsuo Endoh

IPC: G11C11/16

Abstract: A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

公开(公告)号：US11468932B2

公开(公告)日：2022-10-11

申请号：US17254592

申请日：2019-06-20

Applicant: TOHOKU UNIVERSITY

Inventor： Tetsuo Endoh ,  Yoshiaki Saito ,  Shoji Ikeda

IPC: G11C11/16

Abstract: A magnetic memory device includes: a memory cell array including a plurality of lines arranged parallel to one another at predetermined intervals and extending in one direction, and a plurality of memory cells connected to the plurality of lines and arranged in a matrix along an extending direction of the plurality of lines and along an arrangement direction of the plurality of lines, each of the plurality of memory cells including a magnetoresistance effect element; a selection circuit connected to the plurality of lines and configured to select non-adjacent lines that are not adjacent to one another, from the plurality of lines; and a controller connected to the selection circuit and configured to cause the selection circuit to select the non-adjacent lines and allow a write current to flow through the non-adjacent lines simultaneously in writing data on the memory cell array.

公开(公告)号：US20220198247A1

公开(公告)日：2022-06-23

申请号：US17043203

申请日：2019-03-29

Applicant: TOHOKU UNIVERSITY

Inventor： Yitao MA ,  Tetsuo Endoh

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54

Abstract: There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

公开(公告)号：US20220157361A1

公开(公告)日：2022-05-19

申请号：US17430000

申请日：2020-02-15

Applicant: TOHOKU UNIVERSITY

Inventor： Masanori Natsui ,  Daisuke Suzuki ,  Akira Tamakoshi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

IPC: G11C11/16 ,  G06F17/14

Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

公开(公告)号：US11183228B2

公开(公告)日：2021-11-23

申请号：US16647155

申请日：2018-09-14

Applicant: Tohoku University

Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Hideo Ohno ,  Tetsuo Endoh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

公开(公告)号：US11062876B2

公开(公告)日：2021-07-13

申请号：US16360516

申请日：2019-03-21

Applicant: Tohoku University ,  Toray Research Center, Inc.

Inventor： Masaaki Niwa ,  Tetsuo Endoh ,  Shoji Ikeda ,  Kosuke Kimura

IPC: H01J37/22 ,  G01N23/20091 ,  H01J37/28 ,  H01L27/22 ,  H01L43/02

Abstract: An evaluation method for an electronic device provided with an insulating film between a pair of electrode layers includes preparing a sample that has a tunnel barrier insulating film as the insulating film; irradiating the sample with electron beams from a plurality of angles to acquire a plurality of images; and performing image processing using the plurality of images to reconstruct a stereoscopic image and generate a cross-sectional image of the sample from the stereoscopic image.

公开(公告)号：US10957371B2

公开(公告)日：2021-03-23

申请号：US16485289

申请日：2018-02-13

Applicant: Tohoku University

Inventor： Tetsuo Endoh ,  Yasuhiro Ohtomo

IPC: G11C11/22 ,  G11C11/16 ,  G11C13/00

Abstract: A memory device includes a memory cell array in which plural memory cells are arranged in a matrix manner, and a mode selection part. The mode selection part has at least any two of a first mode, a second mode, a third mode and selects any operation mode. The first mode is for reading and writing 1-bit data with the first memory cell or the second memory cell. The second mode is for reading and writing the 1-bit data with a cell unit including the N first memory cells and the N second memory cells connected to a bit line pair. The third mode is for reading and writing the 1-bit data with a cell unit including the M first memory cells and the M second memory cells connected to the bit line pair. M and N are 1 or more integers which are different from each other.