公开(公告)号：US10541154B2

公开(公告)日：2020-01-21

申请号：US15418949

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US20190372000A1

公开(公告)日：2019-12-05

申请号：US16542284

申请日：2019-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L45/00

Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US10431738B2

公开(公告)日：2019-10-01

申请号：US15253887

申请日：2016-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L21/44 ,  H01L29/40 ,  H01L45/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US20190237379A1

公开(公告)日：2019-08-01

申请号：US16382542

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L33/48 ,  H01L21/56 ,  H01L21/311 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L31/0203 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/29 ,  H01L23/28 ,  H01L21/768 ,  H01L21/683 ,  H01L33/52

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

公开(公告)号：US20190131222A1

公开(公告)日：2019-05-02

申请号：US16222118

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/498 ,  H01L23/433 ,  H01L21/48 ,  H01L23/373

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

公开(公告)号：US10276471B2

公开(公告)日：2019-04-30

申请号：US15855305

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/50 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/48 ,  H01L23/28 ,  H01L23/485 ,  H01L23/00 ,  H01L27/146 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.

公开(公告)号：US20190115311A1

公开(公告)日：2019-04-18

申请号：US16219981

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/31

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.

公开(公告)号：US10177082B2

公开(公告)日：2019-01-08

申请号：US15823786

申请日：2017-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/373 ,  H01L23/433 ,  H01L23/31

Abstract: A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material is configured to provide a path through which heat generated from the chip is dissipated. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the layer of carbon nano material.

公开(公告)号：US20180090425A1

公开(公告)日：2018-03-29

申请号：US15823786

申请日：2017-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/498 ,  H01L23/373 ,  H01L21/48 ,  H01L23/433 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/4871 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/4334 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material is configured to provide a path through which heat generated from the chip is dissipated. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the layer of carbon nano material.

公开(公告)号：US20180026067A1

公开(公告)日：2018-01-25

申请号：US15216815

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Wen Lee ,  Kazuaki Hashimoto ,  Kuo-Chung Yee

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/02379 ,  H01L2224/13024 ,  H01L2224/14135 ,  H01L2924/1433 ,  H01L2924/1436

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.