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    Semiconductor memory device and method of manufacturing the same
    98.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07271454B2

    公开(公告)日：2007-09-18

    申请号：US10927638

    申请日：2004-08-27

    Applicant: Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

    Inventor： Yuuichi Hirano ,  Takashi Ipposhi ,  Shigeto Maegawa ,  Koji Nii

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC classification number: H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  Y10S257/903 ,  Y10S257/904

    Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

    Abstract translation: 连接到字线的触点形成在SRAM单元的存取晶体管的栅电极上。 接触通过元件隔离绝缘膜以达到SOI层。 驱动晶体管的体区和存取晶体管的体区通过位于元件隔离绝缘膜下方的SOI层彼此电连接。 因此，存取晶体管是具有通过触点与主体区域连接的栅电极的DTMOS结构，该触点又电连接到驱动晶体管的体区。 因此，可以在抑制用于形成SRAM单元的区域的增加的同时稳定操作。

    Semiconductor device having SOI structure including a load resistor of an sram memory cell
    99.
    发明授权
    Semiconductor device having SOI structure including a load resistor of an sram memory cell 失效
    具有SOI结构的半导体器件包括一个存储单元的负载电阻器

    公开(公告)号：US07256463B2

    公开(公告)日：2007-08-14

    申请号：US10841469

    申请日：2004-05-10

    Applicant: Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

    Inventor： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

    IPC: H01L27/11

    CPC classification number: H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

    Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.

    Abstract translation: 本发明的目的是提供具有SOI结构的半导体器件，其中可以以高稳定性固定由部分隔离区隔离的元件形成区域中的体区的电位。 在由部分氧化膜（31）隔离的元件形成区域中形成包括源极区（51），漏极区（61）和H栅电极（71）的MOS晶体管。 H栅电极（71）将从栅极宽度W方向形成的主体区域（13）与漏极区域（61）和源极区域（51）的源极区域（51）和漏极区域（61）相邻地隔离 ）通过“I”横向（图中的垂直方向），中心“ - ”用作原始MOS晶体管的栅电极。

    Semiconductor device including a capacitance
    100.
    发明申请
    Semiconductor device including a capacitance 失效

    公开(公告)号：US20060289906A1

    公开(公告)日：2006-12-28

    申请号：US11510582

    申请日：2006-08-28

    Applicant: Shigenobu Maeda ,  Takashi Ipposhi ,  Yuuichi Hirano

    Inventor： Shigenobu Maeda ,  Takashi Ipposhi ,  Yuuichi Hirano

    IPC: H01L29/76 ,  H01L21/8234

    CPC classification number: H01L21/84 ,  H01L27/0629 ,  H01L27/0808 ,  H01L27/0811 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/66545 ,  H01L29/94

    Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

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