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    STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS
    92.
    发明申请
    STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS 有权
    用于双通道和N沟道晶体管性能增强的双向应变SOI衬底中的应变变换

    公开(公告)号：US20100301416A1

    公开(公告)日：2010-12-02

    申请号：US12784819

    申请日：2010-05-21

    申请人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

    发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Andy Wei

    IPC分类号： H01L27/12 ,  H01L21/782

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7846

    摘要： In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region.

    摘要翻译： 在先进的SOI器件中，可以在全局应变半导体层的基础上实现高拉伸应变分量，同时通过适当地选择高度 - 长度方面，可以在P沟道晶体管中产生一定的压缩应变 相应活性区的比例。 已经认识到，有效区域中最终获得的应变分布强烈地取决于有源区的纵横比。 因此，通过为N沟道晶体管选择中等的高度 - 长度长宽比，可以保留初始拉伸应变分量的很大一部分。 另一方面，用于P沟道晶体管的中等高度的长宽比可能导致有源区的中心表面区域中的压缩应变分量。

    Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same
    93.
    发明授权
    Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same 有权
    具有嵌入式拉伸应变层的晶体管，其具有减小的偏移到栅电极的方法及其形成方法

    公开(公告)号：US07659213B2

    公开(公告)日：2010-02-09

    申请号：US11566840

    申请日：2006-12-05

    申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

    IPC分类号： H01L21/31 ,  H01L21/42 ,  H01L21/8222

    CPC分类号： C23C8/20 ,  C23C8/80 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing mechanism. The carbon implantation may be preceded by a pre-amorphization implantation, for instance on the basis of silicon. Moreover, by removing a spacer structure used for forming deep drain and source regions, the degree of lateral offset of the strained silicon/carbon material with respect to the gate electrode may be determined substantially independently from other process requirements. Moreover, an additional sidewall spacer used for forming metal silicide regions may be provided with reduced permittivity, thereby additionally contributing to an overall performance enhancement.

    摘要翻译： 通过离子注入和随后的基于闪光或基于激光的退火工艺引入碳，具有拉伸应变的应变硅/碳材料可以紧邻通道区域定位，从而增强应变诱导机制。 可以在碳注入之前进行预非晶化注入，例如基于硅。 此外，通过去除用于形成深漏极和源极区的间隔结构，应变硅/碳材料相对于栅极的横向偏移程度可以基本上独立于其它工艺要求来确定。 此外，用于形成金属硅化物区域的附加侧壁间隔物可以具有降低的介电常数，从而另外有助于整体性能提高。

    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same
    96.
    发明授权
    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same 有权
    包括具有应力沟道区域的场效应晶体管的半导体结构及其形成方法

    公开(公告)号：US07608499B2

    公开(公告)日：2009-10-27

    申请号：US11685847

    申请日：2007-03-14

    申请人： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    发明人： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

    摘要翻译： 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件和第二晶体管元件中的每一个包括栅电极。 在第一晶体管元件和第二晶体管元件上沉积应力材料层。 被施加的材料层被加工成从与第二晶体管元件的栅电极相邻的应力材料层侧壁间隔和覆盖第一晶体管元件的硬掩模形成。 在第二晶体管元件的栅电极附近形成一对空腔。 在空腔中形成一对应力产生元件，并且至少部分地去除硬掩模。

    Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors
    97.
    发明授权
    Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors 有权
    用于增强应力传递到NMOS和PMOS晶体管的沟道区域的技术

    公开(公告)号：US07344984B2

    公开(公告)日：2008-03-18

    申请号：US11468450

    申请日：2006-08-30

    申请人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

    发明人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

    摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

    摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。

    TECHNIQUE FOR FORMING A STRAINED TRANSISTOR BY A LATE AMORPHIZATION AND DISPOSABLE SPACERS
    98.
    发明申请
    TECHNIQUE FOR FORMING A STRAINED TRANSISTOR BY A LATE AMORPHIZATION AND DISPOSABLE SPACERS 有权
    通过最新的制备和可处理的间隔形成应变晶体的技术

    公开(公告)号：US20070202653A1

    公开(公告)日：2007-08-30

    申请号：US11550941

    申请日：2006-10-19

    申请人： Jan Hoentschel ,  Andy Wei ,  Gert Burbach ,  Peter Javorka

    发明人： Jan Hoentschel ,  Andy Wei ,  Gert Burbach ,  Peter Javorka

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7846 ,  H01L21/26506 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78621

    摘要： By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.

    摘要翻译： 通过使用一次性间隔物方法在非晶化过程之前形成漏极和源极区域，以在存在应力间隔层的情况下重新结晶半导体区域，可能与增强的退火技术（例如激光和闪光退火工艺）结合， 可以提供更有效的应变产生机构。 此外，用于形成金属硅化物的间隔物可以具有减小的宽度，从而将相应的金属硅化物区域更靠近沟道区域。 因此，可以基于上述技术获得总体增强的性能。

    Multiple gate transistor having homogenously silicided fin end portions
    99.
    发明授权
    Multiple gate transistor having homogenously silicided fin end portions 有权
    具有均匀硅化鳍片端部的多栅极晶体管

    公开(公告)号：US08791509B2

    公开(公告)日：2014-07-29

    申请号：US12620083

    申请日：2009-11-17

    申请人： Sven Beyer ,  Patrick Press ,  Rainer Giedigkeit ,  Jan Hoentschel

    发明人： Sven Beyer ,  Patrick Press ,  Rainer Giedigkeit ,  Jan Hoentschel

    IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/772

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795

    摘要： In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.

    摘要翻译： 在多栅极晶体管中，晶体管的漏极或源极的多个鳍状物通过公共接触元件彼此电连接，其中相应的接触区域的增强的均匀性可以通过增强的硅化工艺序列来实现。 为此，金箔可以嵌入电介质材料中，其中可以形成适当的接触开口以露出金属丝的端面，其然后可以作为硅化表面区域。