公开(公告)号：US20110121398A1

公开(公告)日：2011-05-26

申请号：US12623683

申请日：2009-11-23

申请人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

发明人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.

摘要翻译： 在制造高级晶体管期间，通过在完成基本晶体管配置之后执行毫秒退火处理可以抑制显着的掺杂剂扩散，其中还可以通过在侧壁间隔结构内形成应变诱导区域来获得应力记忆技术。 由于在间隔结构中形成相应的空隙，所以可以在相邻沟道区域获得高拉伸应变分量。

公开(公告)号：US20120146155A1

公开(公告)日：2012-06-14

申请号：US13401896

申请日：2012-02-22

申请人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

发明人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

IPC分类号： H01L27/092

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.

摘要翻译： 在制造高级晶体管期间，通过在完成基本晶体管配置之后执行毫秒退火处理可以抑制显着的掺杂剂扩散，其中还可以通过在侧壁间隔结构内形成应变诱导区域来获得应力记忆技术。 由于在间隔结构中形成相应的空隙，所以在相邻通道区域中可以获得高拉伸应变分量。

公开(公告)号：US08143133B2

公开(公告)日：2012-03-27

申请号：US12623683

申请日：2009-11-23

申请人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

发明人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.

摘要翻译： 在制造高级晶体管期间，通过在完成基本晶体管配置之后执行毫秒退火处理可以抑制显着的掺杂剂扩散，其中还可以通过在侧壁间隔结构内形成应变诱导区域来获得应力记忆技术。 由于在间隔结构中形成相应的空隙，所以可以在相邻沟道区域获得高拉伸应变分量。

公开(公告)号：US08338885B2

公开(公告)日：2012-12-25

申请号：US13401896

申请日：2012-02-22

申请人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

发明人： Jan Hoentschel ,  Thomas Feudel ,  Ralf Illgen

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

摘要： During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.

摘要翻译： 在制造高级晶体管期间，通过在完成基本晶体管配置之后执行毫秒退火处理可以抑制显着的掺杂剂扩散，其中还可以通过在侧壁间隔结构内形成应变诱导区域来获得应力记忆技术。 由于在间隔结构中形成相应的空隙，所以在相邻通道区域中可以获得高拉伸应变分量。

公开(公告)号：US08623742B2

公开(公告)日：2014-01-07

申请号：US13079341

申请日：2011-04-04

申请人： Stephan Kronholz ,  Matthias Kessler ,  Thomas Feudel

发明人： Stephan Kronholz ,  Matthias Kessler ,  Thomas Feudel

IPC分类号： H01L21/76

CPC分类号： H01L29/78621 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7848

摘要： A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.

摘要翻译： 在晶体管元件中形成应变诱导半导体合金之前，沟槽隔离结构的材料损耗的减少可以导致例如相对于驱动电流和阈值电压的优异的器件均匀性。 为此，当形成浅沟槽隔离时，可以省略使用稀释氢氟酸的至少一个蚀刻工艺，同时提供与常规工艺策略的高度兼容性。

公开(公告)号：US08288256B2

公开(公告)日：2012-10-16

申请号：US12023743

申请日：2008-01-31

申请人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

发明人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

摘要： By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

摘要翻译： 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

公开(公告)号：US07625802B2

公开(公告)日：2009-12-01

申请号：US10400226

申请日：2003-03-27

申请人： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

发明人： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/1083

摘要： A method of forming the halo structures of a field effect transistor is disclosed. The halo structures are formed by implanting ions of a dopant material into the substrate on which the transistor is to be formed, wherein the tilt angle of the ion beam with respect to the surface of the substrate is varied according to a predefined time schedule comprising a plurality of implanting periods.

摘要翻译： 公开了形成场效应晶体管的光晕结构的方法。 卤素结构通过将掺杂剂材料的离子注入到其上将形成晶体管的衬底中而形成，其中离子束相对于衬底的表面的倾斜角度根据包括 多个植入期。

公开(公告)号：US07419867B2

公开(公告)日：2008-09-02

申请号：US11154878

申请日：2005-06-16

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

IPC分类号： H01L21/8238

CPC分类号： H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.

摘要翻译： 通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。 掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。

公开(公告)号：US06821887B2

公开(公告)日：2004-11-23

申请号：US10391243

申请日：2003-03-18

申请人： Karsten Wieczorek ,  Stephan Kruegel ,  Manfred Horstmann ,  Thomas Feudel

发明人： Karsten Wieczorek ,  Stephan Kruegel ,  Manfred Horstmann ,  Thomas Feudel

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507

摘要： The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

摘要翻译： MOS晶体管的多晶硅栅电极可以基本上完​​全转变为金属硅化物，而不牺牲漏极和源极结，因为用于形成栅电极的多晶硅层的厚度被靶向为基本上转化为金属硅化物 随后的硅化工艺。 基本上由金属硅化物组成的栅极电极甚至在深亚微米范围内的临界尺寸下也提供高导电性，同时多晶硅栅极耗尽的效果显着降低。 具有基本上完全转换的金属硅化物栅电极的MOS晶体管的制造基本上与标准MOS工艺技术相兼容。

公开(公告)号：US06808970B2

公开(公告)日：2004-10-26

申请号：US10602583

申请日：2003-06-24

申请人： Thomas Feudel ,  Christian Krueger ,  Lutz Herrmann

发明人： Thomas Feudel ,  Christian Krueger ,  Lutz Herrmann

IPC分类号： H01L21338

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/7842

摘要： A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

摘要翻译： 公开了一种用于制造场效应晶体管的制造工艺，包括在其上制造晶体管的衬底的表面上产生应变表面层。 应变表面层是通过将氙和/或其它重的惰性离子注入衬底而产生的。 可以在栅极氧化物生长之后或之前进行植入。 之后的处理与传统的MOS技术一样进行。 假设应变表面层改善了晶体管的沟道迁移率。