公开(公告)号：US07155598B2

公开(公告)日：2006-12-26

申请号：US10144592

申请日：2002-05-09

申请人： G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/38

CPC分类号： G06F9/30189 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3842

摘要： A conditional execution apparatus in a microprocessor is provided. The conditional execution apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies a condition, where execution of an operation prescribed by the extended instruction depends upon realization of the condition. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for the microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and evaluates the condition. If the condition is not realized, then the extended execution logic precludes execution of the operation.

公开(公告)号：US07055022B1

公开(公告)日：2006-05-30

申请号：US10279216

申请日：2002-10-22

申请人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

IPC分类号： G06F9/22

CPC分类号： G06F9/322 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/324

摘要： A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives an indirect near jump macro instruction, and generates a load-jump micro instruction, where the load-jump micro instruction directs load logic to retrieve an offset and directs the execution logic to generate a target address. The load logic is coupled to the paired operation translation logic and receives the load-jump micro instruction. The load logic retrieves the offset from memory, where the offset indicates a jump destination that is relative to an instruction address corresponding to the indirect near jump macro instruction. The execution logic is coupled to the load logic. The execution logic receives the offset, and employs the instruction address and the offset to generate the target address specifying the jump destination for the near jump operation.

摘要翻译： 提供了一种微处理器装置，用于执行包括成对的操作转换逻辑，负载逻辑和执行逻辑的间接近跳转操作。 配对的操作转换逻辑接收间接近跳宏指令，并产生负载跳转微指令，其中负载跳转微指令指示负载逻辑以检索偏移并引导执行逻辑以产生目标地址。 负载逻辑耦合到成对的操作转换逻辑并接收负载跳转微指令。 负载逻辑从存储器检索偏移量，其中偏移量表示相对于间接近跳宏指令对应的指令地址的跳转目的地。 执行逻辑耦合到负载逻辑。 执行逻辑接收偏移量，并采用指令地址和偏移量来生成指定近跳操作的跳转目的地的目标地址。

公开(公告)号：US06697937B1

公开(公告)日：2004-02-24

申请号：US10353203

申请日：2003-01-28

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F938

CPC分类号： G06F9/3806 ,  G06F9/3844

摘要： An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions where the first branch instructions are categorized within the first table according to a first outcome bias. The second table stores branch histories for a second set of branch instructions, where the second branch instructions are categorized within the second table according to a second outcome bias. The selection logic is coupled to the first and second tables. When a branch instruction is executed by the microprocessor, the selection logic selects a particular branch history to predict the outcome of the branch instruction. Thus, a branch prediction is made based upon contents of a branch history that is selected from a table containing branch histories for other branch instructions that are categorized according to similar outcome bias, thereby reducing the negative effects of aliasing.

摘要翻译： 提供了一种装置和方法，用于在流水线微处理器执行之前准确预测分支指令的结果。 该装置包括第一表，第二表和选择逻辑。 第一表存储第一组分支指令的分支历史，其中第一分支指令根据第一结果偏差在第一表格内被分类。 第二表存储第二组分支指令的分支历史，其中根据第二结果偏差将第二分支指令分类在第二表中。 选择逻辑耦合到第一和第二表。 当微处理器执行分支指令时，选择逻辑选择特定分支历史以预测分支指令的结果。 因此，基于从包含根据类似结果偏差分类的其他分支指令的分支历史的表中选择的分支历史的内容进行分支预测，从而减少混叠的负面影响。

公开(公告)号：US06519696B1

公开(公告)日：2003-02-11

申请号：US09538314

申请日：2000-03-30

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F9302

CPC分类号： G06F9/30032 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/384 ,  G06F9/3853

摘要： An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of floating point operations common to most floating point software algorithms where floating point exchange operations appear as every other instruction between floating point computational instructions. The apparatus includes translation logic, that pairs the operations directed by a floating point macro instruction and a floating point exchange macro instruction by generating a micro instruction with an exchange extension. The exchange extension directs the microprocessor to perform the floating point exchange operation in parallel with the operation prescribed by the floating point macro instruction within a single floating point unit. The apparatus also has floating point register logic that receives the micro instruction and exchange extension, and which performs the floating point exchange operation in parallel with the operation directed by the micro instruction.

摘要翻译： 提供了一种用于在零有效时钟周期中在流水线微处理器中执行浮点交换操作的装置和方法。 本发明利用大多数浮点软件算法共同的浮点运算模式，其中浮点交换操作在浮点计算指令之间出现为每隔一个指令。 该装置包括翻译逻辑，其通过产生具有交换扩展的微指令来对对由浮点宏指令和浮点交换宏指令引导的操作。 交换扩展指示微处理器与单个浮点单元中的浮点宏指令所规定的操作并行执行浮点交换操作。 该装置还具有接收微指令和交换扩展的浮点寄存器逻辑，并且与由微指令执行的操作并行执行浮点交换操作。

公开(公告)号：US06499101B1

公开(公告)日：2002-12-24

申请号：US09272225

申请日：1999-03-18

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F900

CPC分类号： G06F9/3846 ,  G06F9/3848

摘要： An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a static branch predictor, a prediction correlator, and branch history update logic. If a branch instruction is known to exhibit a bias toward a particular outcome, then the static branch predictor directs the microprocessor, via a precedence signal, to take the particular outcome, regardless of what a dynamic branch prediction for the branch instruction may indicate. Thus, the predicted outcome takes precedence over the dynamic branch prediction for a biased outcome branch instruction. The branch history update logic updates a branch history entry corresponding to a branch instruction following its resolution, unless the precedence signal indicates that a particular outcome for the branch instruction was directed by the static branch predictor. In this case the corresponding branch history entry is not updated.

摘要翻译： 提供了一种装置和方法，用于在流水线微处理器执行之前准确预测分支指令的结果。 该装置包括静态分支预测器，预测相关器和分支历史更新逻辑。 如果已知分支指令对特定结果表现偏见，则静态分支预测器将通过优先信号指导微处理器采取特定结果，而不管分支指令的动态分支预测是什么。 因此，预测结果优先于偏向结果分支指令的动态分支预测。 分支历史更新逻辑更新与其分辨率之后的分支指令相对应的分支历史条目，除非优先信号指示分支指令的特定结果由静态分支预测器指导。 在这种情况下，相应的分支历史记录条目不被更新。

公开(公告)号：US06247122B1

公开(公告)日：2001-06-12

申请号：US09203884

申请日：1998-12-02

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F942

CPC分类号： G06F9/3846 ,  G06F9/3848

摘要： An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A static branch predictor makes a prediction of the outcome of a conditional branch instruction based on the branch test type and the branch target address displacement sign. A branch history table stores a bit indicating whether the prediction of the static predictor agreed with the outcome of the last execution of the branch instruction. If the history table bit agrees, then the static prediction is used. Otherwise, the opposite of the static prediction is used.

摘要翻译： 提供了一种通过提高条件分支指令的预测精度来提高微处理器性能的装置和方法。 静态分支预测器基于分支测试类型和分支目标地址位移符号来预测条件分支指令的结果。 分支历史表存储指示静态预测符的预测是否与分支指令的最后执行的结果一致的位。 如果历史表位同意，则使用静态预测。 否则，使用静态预测的相反。

公开(公告)号：US5983344A

公开(公告)日：1999-11-09

申请号：US820576

申请日：1997-03-19

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3017 ,  G06F9/3824

摘要： An apparatus and method for improving the execution speed of macro instructions which have an operand located in memory, and where the destination of the result is in memory. The apparatus includes an ALU Store which monitors micro instructions generated by a translator. When a macro instruction is fetched which has an operand located in memory, and the result is to be stored in the same location in memory, the translator generates a LOAD micro instruction followed immediately by an operation micro instruction which contains STORE indicia, such as a STORE suffix. The ALU Store latches the address created by the LOAD micro instruction, and uses this latched address in the following operation store micro instruction.

摘要翻译： 一种用于提高具有位于存储器中的操作数并且结果的目的地在存储器中的宏指令的执行速度的装置和方法。 该装置包括监视由翻译器产生的微指令的ALU存储器。 当获取具有位于存储器中的操作数的宏指令，并且将结果存储在存储器中的相同位置时，转换器产生一个LOAD微指令，紧跟着包含STORE标记的操作微指令，例如 STORE后缀。 ALU存储器锁存由LOAD微指令创建的地址，并在以下操作存储器微指令中使用该锁存地址。

公开(公告)号：US09244686B2

公开(公告)日：2016-01-26

申请号：US14007116

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

摘要翻译： 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US09141389B2

公开(公告)日：2015-09-22

申请号：US13412888

申请日：2012-03-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC分类号： G06F9/30 ,  G06F9/44

CPC分类号： G06F9/30123 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/4403

摘要： A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.

摘要翻译： 能够运行x86指令集架构（ISA）机器语言程序和高级RISC机器（ARM）的微处理器ISA机器语言程序包括指示微处理器当前是否正在获取x86 ISA或ARM ISA机器语言程序的指令的模式指示器 和多个硬件寄存器。 当模式指示灯指示微处理器当前正在获取x86 ISA机器语言程序指令时，多个硬件寄存器存储x86 ISA架构状态; 当模式指示灯指示微处理器当前正在获取ARM ISA机器语言程序指令时，多个硬件寄存器存储ARM ISA架构状态。

公开(公告)号：US08819839B2

公开(公告)日：2014-08-26

申请号：US12263250

申请日：2008-10-31

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06Q99/00 ,  G06F21/74 ,  G06F21/72 ,  G06F21/79

CPC分类号： G06F21/74 ,  G06F21/72 ,  G06F21/79

摘要： An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus, and the secure application program is executed in a secure execution mode. The microprocessor has a watchdog manager that monitors environments of the microprocessor by noting and evaluating data communicated by a plurality of monitors, and that classifies the data to indicate a security level associated with execution of the secure application program, and that directs secure execution mode logic to perform responsive actions in accordance with the security level. The secure non-volatile memory is coupled to the microprocessor via a private bus, and stores the secure application program. The secure application program is encrypted. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor.

摘要翻译： 一种包括微处理器和安全非易失性存储器的装置。 微处理器执行非安全应用程序和安全应用程序。 通过系统总线从系统存储器访问非安全应用程序，并且以安全执行模式执行安全应用程序。 微处理器具有监视器管理器，其通过注意和评估由多个监视器传送的数据来监视微处理器的环境，并且对数据进行分类以指示与执行安全应用程序相关联的安全级别，并且指导安全执行模式逻辑 根据安全级别执行响应动作。 安全的非易失性存储器经由专用总线耦合到微处理器，并存储安全应用程序。 安全应用程序被加密。 专用总线上的交易与系统总线和微处理器内相应的系统总线资源隔离。