公开(公告)号：US07335911B2

公开(公告)日：2008-02-26

申请号：US10848189

申请日：2004-05-18

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yasuyuki Arai

IPC分类号： H01L29/04

CPC分类号： H01L27/1222 ,  G02F1/13454 ,  H01L21/32136 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78645 ,  H01L2029/7863

摘要： By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

摘要翻译： 通过根据电路所要求的功能，在半导体器件的各种电路中设置适当的TFT结构，可以提高半导体器件的工作性能和可靠性，降低功耗并降低制造成本 并通过减少处理步骤的数量来提高产量。 TFT的LDD区域形成为具有用于控制导电性的杂质元素的浓度梯度，该杂质元素随着与漏极区的距离减小而变高。 为了形成具有杂质元素的浓度梯度的这样的LDD区域，本发明使用了具有锥形部的栅电极的方法，从而掺杂电离杂质元素，以控制在电场中加速的电导率，从而 其穿过栅电极和栅绝缘膜进入半导体层。

公开(公告)号：US20070272989A1

公开(公告)日：2007-11-29

申请号：US11752437

申请日：2007-05-23

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L29/78

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66598 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

摘要翻译： 在诸如有源矩阵显示器的半导体器件的制造中，在光刻中对抗蚀剂掩模进行图案化的需要增加了制造工艺中的步骤数量和完成它们所需的时间，因此代表了大量成本。 本发明提供了一种用于在半导体层中以自对准的方式将杂质元素掺杂到半导体层303中以形成两层栅电极的上层（第二导电膜306）作为掩模来形成杂质区的方法。 杂质元素通过栅电极（第一导电膜305）的下层，并通过栅极绝缘膜304掺杂到半导体层中。 通过这种方式，在半导体层303中形成GOLD结构的LDD区域313。

公开(公告)号：US07294887B2

公开(公告)日：2007-11-13

申请号：US11337514

申请日：2006-01-24

申请人： Hideomi Suzawa ,  Koji Ono ,  Hideto Ohnuma ,  Hirokazu Yamagata ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Koji Ono ,  Hideto Ohnuma ,  Hirokazu Yamagata ,  Shunpei Yamazaki

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： G02F1/13454 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L2029/7863

摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.

摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。

公开(公告)号：US20070013859A1

公开(公告)日：2007-01-18

申请号：US11525016

申请日：2006-09-22

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC分类号： C30B33/00 ,  G02F1/1339

CPC分类号： H01L29/4908 ,  G02F2001/13629 ,  H01L23/5283 ,  H01L23/53223 ,  H01L27/3241 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648 ,  H01L51/5203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00

摘要： The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.

公开(公告)号：US07026194B2

公开(公告)日：2006-04-11

申请号：US10317064

申请日：2002-12-12

申请人： Hideomi Suzawa ,  Koji Ono ,  Hideto Ohnuma ,  Hirokazu Yamagata ,  Shunpei Yamazaki

发明人： Hideomi Suzawa ,  Koji Ono ,  Hideto Ohnuma ,  Hirokazu Yamagata ,  Shunpei Yamazaki

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： G02F1/13454 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L2029/7863

摘要： TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.

摘要翻译： 布置在各种电路中的TFT具有适于电路功能的结构，以便提高半导体器件的操作特性和可靠性，降低电力消耗，减少步数，降低生产成本和改善 产量。 用于控制TFT的LDD区域622和623中的导电类型的杂质元素的浓度梯度使得浓度朝着漏极区增加。 为此，形成锥形栅电极607和锥形栅极绝缘膜605，并且用于控制导电类型的电离杂质元件通过栅极绝缘膜605添加到半导体层。

公开(公告)号：US06992328B2

公开(公告)日：2006-01-31

申请号：US10664615

申请日：2003-09-19

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yasuyuki Arai

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/42384 ,  G02F1/13454 ,  H01L27/124 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78645 ,  H01L2029/7863

摘要： By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

公开(公告)号：US06984550B2

公开(公告)日：2006-01-10

申请号：US10718584

申请日：2003-11-24

申请人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

发明人： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

摘要： There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

公开(公告)号：US06981336B2

公开(公告)日：2006-01-03

申请号：US10948797

申请日：2004-09-24

申请人： Etsushi Nagae ,  Hiroshi Mukaiyama ,  Koji Ono ,  Masaya Tadano ,  Tetsuya Masuda ,  Kazuyoshi Tomochika ,  Takahiro Nakamura ,  Masakatsu Morishige ,  Harumi Takeuchi ,  Kiyokazu Fujikawa ,  Tamotsu Kawamura ,  Motohiko Kosano ,  Shinichi Akiyama ,  Nobuo Koumoto

发明人： Etsushi Nagae ,  Hiroshi Mukaiyama ,  Koji Ono ,  Masaya Tadano ,  Tetsuya Masuda ,  Kazuyoshi Tomochika ,  Takahiro Nakamura ,  Masakatsu Morishige ,  Harumi Takeuchi ,  Kiyokazu Fujikawa ,  Tamotsu Kawamura ,  Motohiko Kosano ,  Shinichi Akiyama ,  Nobuo Koumoto

IPC分类号： F26B21/06 ,  F26B11/02

CPC分类号： D06F58/206 ,  D06F25/00

摘要： There is disclosed a washing/drying machine having a purpose of shortening a time required for a washing operation and improving an operation efficiency, and comprising: an inner drum in which things to be washed are accommodated and in which a washing operation of the things to be washed and a drying operation after end of the washing operation are performed; a water supply passage for supplying water into the inner drum and a drainage passage for discharging the water from the inner drum in the washing operation; a refrigerant circuit in which a compressor, a gas cooler, an expansion valve, an evaporator and the like are successively connected to one another in an annular form via a piping and in which carbon dioxide is used as a refrigerant; and a blower for blowing air which has exchanged heat with the gas cooler into the inner drum to allow the air passed through the inner drum to exchange the heat with the evaporator in the drying operation.

摘要翻译： 公开了一种洗涤/干燥机，其目的是缩短洗涤操作所需的时间并提高操作效率，并且包括：容纳洗涤物的内筒，其中物品的洗涤操作 洗涤，洗涤操作结束后进行干燥处理; 用于将水供给到内筒的供水通道和用于在洗涤操作中从内筒排出水的排水通道; 其中压缩机，气体冷却器，膨胀阀，蒸发器等经由管道彼此连续地连接并使用二氧化碳作为制冷剂的制冷剂回路; 以及鼓风机，其将与气体冷却器进行热交换的空气吹送到内筒中，以允许在干燥操作中通过内滚筒的空气与蒸发器交换热量。

公开(公告)号：US20050086824A1

公开(公告)日：2005-04-28

申请号：US10878638

申请日：2004-06-29

申请人： Koji Ono ,  Masahisa Otake ,  Masaya Tadano ,  Etsushi Nagae ,  Hiroshi Mukaiyama

发明人： Koji Ono ,  Masahisa Otake ,  Masaya Tadano ,  Etsushi Nagae ,  Hiroshi Mukaiyama

IPC分类号： D06F25/00 ,  D06F58/02 ,  D06F58/20 ,  D06F58/24 ,  D06F58/28 ,  F25B9/00 ,  F26B11/04 ,  F26B21/04 ,  F26B19/00

CPC分类号： D06F58/206 ,  D06F58/24 ,  D06F58/28 ,  D06F2058/287 ,  F25B9/008 ,  F25B2309/061

摘要： An object in a drier is to reduce a cooling time after completion of a drying operation and improve operation efficiency. The dryer comprises a storage room to accommodate a drying target and performs the drying operation and a cooling operation after completion of the drying operation for the drying target in the storage room. The dryer comprises: a refrigerant circuit configured by sequentially connecting, with a pipe in a circular form, a compressor, a radiator, a pressure reducing device, an evaporator and the like; an air circulation path for circulating, by an air blower, air from the radiator into the evaporator through the storage room; and an external radiator provided outside the air circulation path, wherein in the drying operation, a refrigerant discharged from the compressor flows to the radiator to release heat, and is pressure reduced by the pressure reducing device, and is then evaporated by the evaporator, and in the cooling operation, the refrigerant discharged from the compressor flows to the external radiator to release heat, and is pressure reduced by the pressure reducing device, and is then evaporated by the evaporator.

摘要翻译： 干燥器中的一个目的是在干燥操作完成之后减少冷却时间并提高操作效率。 干燥机包括容纳干燥目标的储藏室，并且在完成了储藏室中的干燥目标的干燥操作之后执行干燥操作和冷却操作。 干燥机包括：制冷剂回路，其通过以圆形形式的管连续地连接压缩机，散热器，减压装置，蒸发器等构成; 空气循环路径，用于通过鼓风机将来自散热器的空气通过储藏室循环到蒸发器中; 以及设置在空气循环路径的外部的外部散热器，其中在干燥操作中，从压缩机排出的制冷剂流向散热器以释放热量，并通过减压装置降压，然后由蒸发器蒸发， 在制冷运转中，从压缩机排出的制冷剂流向外部散热器，以释放热量，并通过减压装置进行减压，然后被蒸发器蒸发。

公开(公告)号：US20050040403A1

公开(公告)日：2005-02-24

申请号：US10960015

申请日：2004-10-08

申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama

IPC分类号： H01L21/30 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/66757 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66598 ,  H01L29/78621 ,  H01L2029/7863

摘要： In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

摘要翻译： 在诸如有源矩阵显示器的半导体器件的制造中，在光刻中对抗蚀剂掩模进行图案化的需要增加了制造工艺中的步骤数量和完成它们所需的时间，因此代表了大量成本。 本发明提供了一种用于在半导体层中以自对准的方式将杂质元素掺杂到半导体层303中以形成两层栅电极的上层（第二导电膜306）作为掩模来形成杂质区的方法。 杂质元素通过栅电极的下层（第一导电膜305）掺杂到半导体层中，并通过栅极绝缘膜304掺杂。通过这种方式，在半导体中形成GOLD结构的LDD区域313 层303。