公开(公告)号：US20110140288A1

公开(公告)日：2011-06-16

申请号：US12638557

申请日：2009-12-15

申请人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

发明人： Haining Yang ,  Chock H. Gan ,  Zhongze Wang ,  Beom-Mo Han

IPC分类号： H01L23/50 ,  H01L21/3205

CPC分类号： H01L27/0207 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.

摘要翻译： 一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。 集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。 导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。 导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

公开(公告)号：US07816219B2

公开(公告)日：2010-10-19

申请号：US11850076

申请日：2007-09-05

申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

摘要翻译： 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

公开(公告)号：US07737014B2

公开(公告)日：2010-06-15

申请号：US10596249

申请日：2003-12-08

申请人： Frederick William Buehrer ,  Dureseti Chidambarrao ,  Bruce B. Doris ,  Hsiang-Jen Huang ,  Haining Yang

发明人： Frederick William Buehrer ,  Dureseti Chidambarrao ,  Bruce B. Doris ,  Hsiang-Jen Huang ,  Haining Yang

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

摘要翻译： 应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率， 从而改变最终的硼浓度。 在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

公开(公告)号：US07732270B2

公开(公告)日：2010-06-08

申请号：US11972964

申请日：2008-01-11

申请人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US07678658B2

公开(公告)日：2010-03-16

申请号：US12018440

申请日：2008-01-23

申请人： Haining Yang ,  Robert C. Wong

发明人： Haining Yang ,  Robert C. Wong

IPC分类号： H01L21/20

CPC分类号： H01L27/1104 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1203

摘要： A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the portion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.

摘要翻译： 提供了形成改进的静态随机存取存储器（SRAM）互连结构的方法。 该方法包括在形成在半导体衬底的硅层上的图案化多晶硅层的周围形成侧壁隔离物; 去除图案化的多晶硅层以暴露盖层的一部分; 蚀刻盖层的暴露部分以露出硅层的一部分; 蚀刻硅层的部分，其中所述硅层的一部分将所述SRAM的下拉器件的至少一部分连接到所述SRAM的上拉器件的至少一部分; 形成栅极氧化物; 以及在所述栅极氧化物上形成栅极导体。 还提供互连结构。

公开(公告)号：US07550351B2

公开(公告)日：2009-06-23

申请号：US11538850

申请日：2006-10-05

申请人： Haining Yang ,  Xiangdong Chen

发明人： Haining Yang ,  Xiangdong Chen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/331

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L27/092

摘要： The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gate material doped with first ions for a first device and second gate electrode region comprised of gate material doped with second ions for a second device. The respectively doped regions are connected by a silicide layer near the top surface of the gate conductors.

摘要翻译： 本发明涉及减少掺杂剂交叉扩散并改善芯片密度的改进的晶体管。 本发明的第一实施例包括在由掺杂有用于第一器件的第一离子的栅极材料构成的第一栅极电极区域和由掺杂有第二离子的栅极材料构成的第二栅极电极区域的第一栅极电极区域处部分去除的栅电极材料，用于第二器件 。 分别掺杂的区域通过靠近栅极导体的顶表面的硅化物层连接。

公开(公告)号：US07544608B2

公开(公告)日：2009-06-09

申请号：US11458464

申请日：2006-07-19

申请人： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

发明人： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.

摘要翻译： 一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。 该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。 半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

公开(公告)号：US20080293257A1

公开(公告)日：2008-11-27

申请号：US12186923

申请日：2008-08-06

申请人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。 高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。 每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

公开(公告)号：US07442611B2

公开(公告)日：2008-10-28

申请号：US11657154

申请日：2007-01-24

申请人： Victor W. C. Chan ,  Yong M. Lee ,  Haining Yang

发明人： Victor W. C. Chan ,  Yong M. Lee ,  Haining Yang

IPC分类号： H01L21/8234

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/665

摘要： A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

摘要翻译： 提供了制造半导体器件结构的方法。 在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。 可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。 期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与 离子注入。 然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。 以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。 应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。

公开(公告)号：US20080251934A1

公开(公告)日：2008-10-16

申请号：US11734931

申请日：2007-04-13

申请人： Jack Allan Mandelman ,  Haining Yang

发明人： Jack Allan Mandelman ,  Haining Yang

IPC分类号： H01L29/267 ,  H01L21/3205

CPC分类号： H01L27/11 ,  H01L21/76889 ,  H01L21/76895 ,  H01L27/1104

摘要： Semiconductor device structures and methods of fabricating such semiconductor device structures for use in static random access memory (SRAM) devices. The semiconductor device structure comprises a dielectric region disposed between first and second semiconductor regions and a gate conductor structure extending between the first and second semiconductor regions. The gate conductor structure has a first sidewall overlying the first semiconductor region. The device structure further comprises an electrically connective bridge extending across the first semiconductor region. The electrically connective bridge has a portion that electrically connects a impurity-doped region in the first semiconductor region with the first sidewall of the gate conductor structure.

摘要翻译： 用于制造用于静态随机存取存储器（SRAM）器件的这种半导体器件结构的半导体器件结构和方法。 半导体器件结构包括设置在第一和第二半导体区域之间的介质区域和在第一和第二半导体区域之间延伸的栅极导体结构。 栅极导体结构具有覆盖第一半导体区域的第一侧壁。 器件结构还包括延伸跨越第一半导体区域的电连接桥。 电连接桥具有将第一半导体区域中的杂质掺杂区域与栅极导体结构的第一侧壁电连接的部分。