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公开(公告)号：US08736732B2
公开(公告)日：2014-05-27
申请号：US12722121
申请日：2010-03-11
IPC分类号： H04N5/335
CPC分类号： H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
摘要翻译： 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US20130010513A1
公开(公告)日：2013-01-10
申请号：US13621078
申请日：2012-09-15
申请人： Naoya WATANABE , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya WATANABE , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
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公开(公告)号：US08164934B2
公开(公告)日：2012-04-24
申请号：US12720561
申请日：2010-03-09
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译： 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以增加搜索操作速度。
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公开(公告)号：US07804368B2
公开(公告)日：2010-09-28
申请号：US12155876
申请日：2008-06-11
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03K17/063
摘要： The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.
摘要翻译： 本发明提供一种即使在以低电源电压驱动的情况下也能够稳定工作的电流限制型振荡器和使用该振荡器的电荷泵电路。 限流振荡器具有延迟部分，该延迟部分包括多个串联的反相器，用于基于限流电平指示信号来延迟输出脉冲，并且该振荡器还包括至少一个第一晶体管，其限制第一电流 所述逆变器和高电位电源以及限制所述逆变器之间的第二电流和低电位电源的至少一个第二晶体管，其中所述多个逆变器中的至少一个被配置为与所述第一逆变器连接的第一逆变器 并且不与第二晶体管连接，并且多个反相器中的至少另一个被配置为不与第一晶体管连接并与第二晶体管连接的第二反相器。
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公开(公告)号：US20100109761A1
公开(公告)日：2010-05-06
申请号：US12683838
申请日：2010-01-07
IPC分类号： G05F1/10
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US20100033609A1
公开(公告)日：2010-02-11
申请号：US12473876
申请日：2009-05-28
申请人： Hiroshi KATO , Katsumi Dosaka , Fukashi Morishita
发明人： Hiroshi KATO , Katsumi Dosaka , Fukashi Morishita
IPC分类号： H04N5/335
CPC分类号： H04N5/3742 , H04N5/378
摘要： To obtain a solid state imaging device having a data transfer function capable of outputting digital data after A/D conversion to the outside in a high speed.Each of eight stage data blocks in a data bus part has a data line pair and an amplifier part which is coupled to the data line pair. Then, the amplifier part amplifies a signal of the data line pair on an amplifier data line pair to output the amplified signal as block data outputs at timing indicated by an amplifier enable signal and an amplifier control signal. Further, the eight stage data blocks are coupled with each other from the first stage to the last stage so that the preceding stage block data outputs may be provided to the following stage data line pair as block data inputs, respectively.
摘要翻译： 获得具有数据传送功能的固态成像装置，该数据传输功能能够在高速A / D转换到外部之后输出数字数据。 数据总线部分中的八级数据块中的每一个具有数据线对和耦合到数据线对的放大器部分。 然后，放大器部分放大放大器数据线对上的数据线对的信号，以在由放大器使能信号和放大器控制信号指示的定时处输出放大信号作为块数据输出。 此外，八级数据块从第一级到最后级彼此耦合，使得前级级块数据输出可以分别作为块数据输入提供给后级数据线对。
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公开(公告)号：US20090058543A1
公开(公告)日：2009-03-05
申请号：US12289230
申请日：2008-10-23
IPC分类号： G01K7/00
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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公开(公告)号：US07459983B2
公开(公告)日：2008-12-02
申请号：US11452317
申请日：2006-06-14
IPC分类号： G01K7/00
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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99.发明授权Internal voltage generating circuit and semiconductor integrated circuit device 有权内部电压发生电路和半导体集成电路器件公开(公告)号：US07456680B2
公开(公告)日：2008-11-25
申请号：US11135488
申请日：2005-05-24
CPC分类号： G05F1/465
摘要： A voltage for reference at a voltage level higher than a target value is produced from a constant current provided from a constant current generating circuit, and is subjected to resistance division by a resistance division circuit to produce a reference voltage at the target level, and then a final reference voltage is produced by a voltage follower. An internal voltage generating circuit thus provided can generate the reference voltage having the desired voltage level with high accuracy as well as an internal voltage based on the reference voltage by controlling temperature characteristic even with a low power supply voltage.
摘要翻译： 在从恒定电流产生电路提供的恒定电流中产生高于目标值的电压电压的参考电压，并通过电阻分割电路进行电阻分割以产生目标电平的参考电压，然后 最终的参考电压由电压跟随器产生。 由此提供的内部电压产生电路即使在低电源电压下也可以通过控制温度特性，以高精度产生具有所需电压电平的基准电压以及基于参考电压的内部电压。
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公开(公告)号：US20070263466A1
公开(公告)日：2007-11-15
申请号：US11797804
申请日：2007-05-08
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C7/065 , G11C7/08 , G11C7/1048 , G11C11/405 , G11C11/4091 , G11C11/4099 , G11C2207/002 , G11C2207/005 , G11C2207/2281 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/10897 , H01L27/1203 , H01L29/7841
摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).
摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。
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