公开(公告)号：US20110012192A1

公开(公告)日：2011-01-20

申请号：US12892044

申请日：2010-09-28

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

摘要翻译： 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。

公开(公告)号：US20100321987A1

公开(公告)日：2010-12-23

申请号：US12488995

申请日：2009-06-22

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

摘要： A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can comprise reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within a pre-specified range. The refresh process includes determining a data value stored in the selected cell, using for example a destructive read process, and refreshing the data value in the selected cell. The time interval can be measured by detecting timing within the sensing interval of a transition of voltage or current on a bit line across a threshold.

摘要翻译： 具有边缘单元检测和刷新资源的可编程电阻存储器件。 边缘小区检测和刷新可以包括读取所选择的小区，测量在所述读取期间与所选择的小区的电阻相关的时间间隔，以及如果所测量的时间落在预定的范围内，则启用刷新过程。 刷新过程包括使用例如破坏性读取处理确定存储在所选择的单元中的数据值，以及刷新所选择的单元中的数据值。 可以通过检测跨越阈值的位线上的电压或电流的转变的感测间隔内的定时来测量时间间隔。

公开(公告)号：US07811890B2

公开(公告)日：2010-10-12

申请号：US11545575

申请日：2006-10-11

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

摘要： A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

摘要翻译： 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。

公开(公告)号：US20100096689A1

公开(公告)日：2010-04-22

申请号：US12619075

申请日：2009-11-16

申请人： Yen-Hao Shih

发明人： Yen-Hao Shih

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.

摘要翻译： 在非易失性存储器结构中，源极/漏极区域被氮掺杂区域包围。 结果，在氮掺杂区上方的衬底和电荷捕捉层之间的界面被多个氮原子钝化。 氮原子可以提高循环非易失性存储器件的数据保留性能和性能。

公开(公告)号：US20100084624A1

公开(公告)日：2010-04-08

申请号：US12286874

申请日：2008-10-02

申请人： Hsiang-Lan Lung ,  Chieh Fang Chen ,  Yen-Hao Shih ,  Ming Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

发明人： Hsiang-Lan Lung ,  Chieh Fang Chen ,  Yen-Hao Shih ,  Ming Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

摘要翻译： 使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。 具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。 该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。 导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。 此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

公开(公告)号：US20090279349A1

公开(公告)日：2009-11-12

申请号：US12117164

申请日：2008-05-08

申请人： Yen-Hao Shih ,  Chieh Fang Chen ,  Hsiang-Lan Lung

发明人： Yen-Hao Shih ,  Chieh Fang Chen ,  Hsiang-Lan Lung

IPC分类号： G11C11/00

CPC分类号： H01L45/126 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.

摘要翻译： 这里描述了存储器件以及用于操作存储器件的方法。 如本文所述的存储单元包括第一电极和第二电极。 存储单元还包括具有沿第一和第二电极之间的电极间电流路径串联布置的第一和第二有源区的相变材料。

公开(公告)号：US07355897B2

公开(公告)日：2008-04-08

申请号：US11773857

申请日：2007-07-05

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

摘要翻译： 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以 随后的编程和擦除周期中的擦除条件。

公开(公告)号：US07242622B2

公开(公告)日：2007-07-10

申请号：US11359044

申请日：2006-02-22

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

摘要翻译： 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以 随后的编程和擦除周期中的擦除条件。

公开(公告)号：US20070133307A1

公开(公告)日：2007-06-14

申请号：US11359044

申请日：2006-02-22

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

公开(公告)号：US20060131634A1

公开(公告)日：2006-06-22

申请号：US10905194

申请日：2004-12-21

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： H01L21/8238 ,  H01L29/06

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

摘要翻译： 一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。 电荷捕获层和控制栅极设置在衬底上。 电介质层设置在基板，电荷俘获层和控制栅极之间。 源极和漏极设置在电荷俘获层的每一侧上的衬底中。 轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。 掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。 由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。