公开(公告)号：US6064265A

公开(公告)日：2000-05-16

申请号：US146529

申请日：1998-09-03

申请人： Kwang Jun Yun ,  Min Kun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Kwang Jun Yun ,  Min Kun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H03F3/193 ,  H03G1/00 ,  H03G3/30 ,  H03G3/10

CPC分类号： H03F3/193 ,  H03G1/007 ,  H03G3/3042 ,  H03F2200/294 ,  H03F2200/318

摘要： The present invention relates to a gain control circuit for a low-noise amplifier. A gain control circuit of a 2-stage low-noise amplifier comprising an input stage noise matching circuit, an intermediate impedance matching circuit, a gain control circuit, and an output stage impedance matching circuit, said gain control circuit including: a feedback circuit connected to a transistor of second stage of the 2-stage low-noise amplifier, said feedback circuit detecting the amplified signal through the first stage and the second stage, and feeding the signal back through a switch circuit; and an attenuation circuit for compensating the harmonics of the input signal.

摘要翻译： 本发明涉及一种用于低噪声放大器的增益控制电路。 一种包括输入级噪声匹配电路，中间阻抗匹配电路，增益控制电路和输出级阻抗匹配电路的2级低噪声放大器的增益控制电路，所述增益控制电路包括：反馈电路， 到2级低噪声放大器的第二级的晶体管，所述反馈电路通过第一级和第二级检测放大的信号，并通过开关电路将信号反馈; 以及用于补偿输入信号的谐波的衰减电路。

公开(公告)号：US5939954A

公开(公告)日：1999-08-17

申请号：US955378

申请日：1997-10-21

申请人： Min Gun Kim ,  Choong Hwan Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Min Gun Kim ,  Choong Hwan Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H01L23/28 ,  H03H7/38 ,  H01L23/64 ,  H05K7/02

CPC分类号： H03H7/38 ,  H01L2224/45144 ,  H01L2224/48091

摘要： The present invention relates to an equivalent circuit of a package ground terminal paddle which is used to mount a microwave integrated circuit, and more particularly, to an approximate equivalent circuit of the package ground terminal paddle by which the expressions of parasitic components can be easily expanded according to the number of gold wires that are down-bonded to the paddle, by introducing an equivalent circuit structure which takes the impedance component output from each terminal as one common impedance component and grounds the common impedance.

摘要翻译： 本发明涉及一种用于安装微波集成电路的封装接地端子板的等效电路，更具体地说涉及封装接地端子板的近似等效电路，通过该电路可以容易地扩展寄生元件的表达 根据下焊接到焊盘的金线的数量，通过引入等效电路结构，其将来自每个端子的阻抗分量输出作为一个公共阻抗分量并将公共阻抗接地。

公开(公告)号：US5787045A

公开(公告)日：1998-07-28

申请号：US777206

申请日：1996-12-27

申请人： Jae Jin Lee

发明人： Jae Jin Lee

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C11/406 ,  G11C13/00

CPC分类号： G11C11/406 ,  G11C7/1018

摘要： An internal address generator of a semiconductor memory device which can achieve a high speed operation. The internal address generator includes at least two bit counters which input a less significant AND-SUM signal from a less significant bit counter and each input an external address signal of 2 bits or more by 1 bit, commonly responding to an enable signal and a clock signal, each bit counter having: a first pass transistor connected between an output terminal and a first node and being responsive to the clock signal; a first inverter for inverting a logic value from the output terminal; a second pass transistor for transmitting an output signal from the first inverter to the first node; second and third inverters parallel-coupled between the first node and a second node to form a feedback loop; fourth and fifth inverters parallel-coupled between third and fourth nodes to form a feedback loop; a third pass transistor connected between the second and third nodes; a sixth inverter connected between the fourth node and the output terminal; a clock switching part for transmitting the clock signal to the third pass transistor during a counter mode in accordance with logic values of the enable signal and the less significant AND-SUM signal; an address switching part for selectively transmitting an external address signal to the third node in accordance with the logic value of the enable signal; a loop switching part for applying the clock signal to the first pass transistor to drive the first pass transistor complementarily to the third pass transistor, during the count mode and to complementarily drive the first and second pass transistors, during a loading mode, in response to the logic values of the enable signal and the less significant AND-SUM signal; and an AND-SUM operation part for generating an AND-SUM signal by a logic signal on the third node and the less significant AND-SUM signal.

摘要翻译： 一种可实现高速运行的半导体存储器件的内部地址发生器。 内部地址生成器包括至少两个位计数器，其从较低有效位计数器输入较低有效的AND-SUM信号，并且每个输入2位或更多位1位的外部地址信号，通常响应于使能信号和时钟 信号，每个位计数器具有：连接在输出端和第一节点之间并响应于时钟信号的第一级晶体管; 用于使来自所述输出端的逻辑值反相的第一反相器; 第二传输晶体管，用于将来自第一反相器的输出信号传输到第一节点; 第二和第三反相器并联耦合在第一节点和第二节点之间以形成反馈回路; 第四和第五反相器并联耦合在第三和第四节点之间以形成反馈回路; 连接在第二和第三节点之间的第三传输晶体管; 连接在第四节点和输出端之间的第六反相器; 时钟切换部分，用于根据使能信号和较低有效AND-SUM信号的逻辑值在计数器模式期间将时钟信号传输到第三传输晶体管; 地址切换部分，用于根据使能信号的逻辑值选择性地将外部地址信号发送到第三节点; 环路切换部分，用于在计数模式期间将时钟信号施加到第一传输晶体管以驱动第一传输晶体管与第三传输晶体管互补，并且在加载模式期间对第一和第二传输晶体管进行补偿，响应于 使能信号的逻辑值和较不重要的AND-SUM信号; 以及AND-SUM操作部分，用于通过第三节点上的逻辑信号和较不重要的AND-SUM信号来产生AND-SUM信号。

公开(公告)号：US5751653A

公开(公告)日：1998-05-12

申请号：US867455

申请日：1997-06-02

申请人： In Sool Chung ,  Jae Jin Lee

发明人： In Sool Chung ,  Jae Jin Lee

IPC分类号： G11C11/407 ,  G11C11/34 ,  G11C11/406 ,  G11C11/408 ,  G11C13/00

CPC分类号： G11C11/4087 ,  G11C11/4085

摘要： A DRAM with reduced leakage current includes at least two line driving means for transmitting high potential to a line selected by an address signal externally input; a main power line for transmitting a power source voltage externally supplied; secondary power lines for transmitting the power source voltage to the respective line driving means; switching means respectively connected between the main power line and secondary power lines; block selection means for outputting a signal where two block selection addresses are logically combined, to each of the line driving means, in order to select and operate one of the line driving means; and switching control means for outputting a signal which controls each of the switching means through the logical combination of the output signal of the block selection means and a refresh operation mode signal.

摘要翻译： 具有减小的漏电流的DRAM包括用于将高电位传输到由外部输入的地址信号选择的线路的至少两个线路驱动装置; 用于发送外部电源电压的主电力线; 用于将电源电压发送到各线路驱动装置的二次电力线路; 分别连接在主电力线和二次电力线之间的开关装置; 块选择装置，用于将两个块选择地址逻辑地组合的信号输出到每个线路驱动装置，以便选择和操作线路驱动装置之一; 以及切换控制装置，用于通过块选择装置的输出信号和刷新操作模式信号的逻辑组合输出控制每个切换装置的信号。

公开(公告)号：US5742185A

公开(公告)日：1998-04-21

申请号：US670840

申请日：1996-06-28

申请人： Jae Jin Lee

发明人： Jae Jin Lee

IPC分类号： G11C11/407 ,  G11C7/10 ,  H03K17/16

CPC分类号： G11C7/1048

摘要： A data bus drive circuit for a semiconductor memory device, comprising true and complementary data buses for transferring true and complementary data from outside of the semiconductor memory device or from memory cells in the semiconductor memory device, respectively, a first control line for inputting an external read/write control signal, a second control line for inputting an external precharge command signal, a read precharge circuit for switching a voltage from a first voltage source to the true and complementary data buses in response to the read/write control signal from the first control line, a write precharge circuit for switching a voltage from a second voltage source to the true and complementary data buses in response to the read/write control signal from the first control line, and a control circuit for selectively applying the read/write control signal from the first control line to the read and write precharge circuits in response to the precharge command signal from the second control line. According to the present invention, the data bus can be precharged with half a supply voltage after a write operation is performed. Therefore, the data bus drive circuit can enhance the operation speed of the semiconductor memory device and reduce power consumption thereof.

摘要翻译： 一种用于半导体存储器件的数据总线驱动电路，包括用于从半导体存储器件外部或半导体存储器件中的存储单元传送真实和互补数据的真实和互补的数据总线，用于输入外部的第一控制线 读/写控制信号，用于输入外部预充电指令信号的第二控制线，用于响应于来自第一电压源的读/写控制信号将电压从第一电压源切换到真互补数据总线的读预充电电路 控制线，用于响应于来自第一控制线的读/写控制信号将来自第二电压源的电压切换到真和互补数据总线的写预充电电路，以及用于选择性地应用读/写控制 响应于来自th的预充电命令信号从第一控制线到读和写预充电电路的信号 e第二控制线。 根据本发明，在执行写入操作之后，数据总线可以被预充电一半的电源电压。 因此，数据总线驱动电路可以提高半导体存储器件的操作速度并降低其功耗。