公开(公告)号：US06218691B1

公开(公告)日：2001-04-17

申请号：US09343096

申请日：1999-06-29

Applicant: In Sool Chung ,  Seong Dong Kim

Inventor： In Sool Chung ,  Seong Dong Kim

IPC: H01L31062

CPC classification number: H01L27/14609 ,  H01L27/14601 ,  H01L27/1463 ,  H01L27/14683

Abstract: The present invention is to provide an image sensor, including: a semiconductor substrate of a first conductive type: a peripheral circuit formed on a first region of the semiconductor substrate, wherein a ground voltage level is applied to the first region; a unit pixel array having a plurality of unit pixels formed on a second region of the semiconductor substrate, wherein the first region is isolated from the second region and wherein a negative voltage level is applied to the second region; and a negative voltage generator for providing the negative voltage for the second region.

Abstract translation: 本发明提供一种图像传感器，包括：第一导电类型的半导体衬底：形成在半导体衬底的第一区域上的外围电路，其中对第一区域施加接地电压电平; 具有形成在所述半导体衬底的第二区域上的多个单位像素的单位像素阵列，其中所述第一区域与所述第二区域隔离，并且其中负电压电平施加到所述第二区域; 以及用于为第二区域提供负电压的负电压发生器。

公开(公告)号：US5940710A

公开(公告)日：1999-08-17

申请号：US610887

申请日：1996-03-05

Applicant: In Sool Chung ,  Young Tag Woo

Inventor： In Sool Chung ,  Young Tag Woo

IPC: H01L21/335 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66575 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor wherein source/drain junctions are formed by depositing and etching an oxide film having a desired thickness prior to the formation of a pocket region carried out by a pocket ion implantation after forming a gate oxide film and gate electrode on a channel region formed by implanting impurity ions in a silicon substrate. The pocket region is formed by impurity ions in source/drain regions exposed by etching the oxide film. Accordingly, it is possible to reduce the thermal budget applied to the source/drain junctions. As a result, the lateral diffusion of the impurity ions implanted in the source/drain junctions can be suppressed as much as possible. That is, the transistor fabricated in accordance with the present invention has a channel length longer than that obtained in accordance with the prior art. Accordingly, the transistor can have a highly compact or densely integrated size. Since source/drain electrodes are separately formed from each other in accordance with the present invention, the insulation between the source/drain electrodes can be effectively obtained.

Abstract translation: 一种用于制造金属氧化物半导体场效应晶体管的方法，其中通过在形成栅极氧化膜之后通过口袋离子注入形成袋状区域之后沉积和蚀刻具有所需厚度的氧化膜形成源极/漏极结 以及通过在硅衬底中注入杂质离子形成的沟道区上的栅电极。 通过蚀刻氧化膜而暴露的源极/漏极区域中的杂质离子形成口袋区域。 因此，可以减少施加到源极/漏极结的热量预算。 结果，可以尽可能地抑制注入在源极/漏极结中的杂质离子的横向扩散。 也就是说，根据本发明制造的晶体管具有比根据现有技术获得的晶体管长度的沟道长度。 因此，晶体管可以具有高度紧凑或密集集成的尺寸。 由于源/漏电极根据本发明彼此分开形成，所以可以有效地获得源/漏电极之间的绝缘。

公开(公告)号：US06853044B1

公开(公告)日：2005-02-08

申请号：US09691784

申请日：2000-10-18

Applicant: In Sool Chung ,  Seong Dong Kim

Inventor： In Sool Chung ,  Seong Dong Kim

IPC: H01L27/146 ,  H01L31/00

CPC classification number: H01L27/14601 ,  H01L27/14609 ,  H01L27/1463

Abstract: The present invention is to provide an image sensor, including: a semiconductor substrate of a first conductive type: a peripheral circuit formed on a first region of the semiconductor substrate, wherein a ground voltage level is applied to the first region; a unit pixel array having a plurality of unit pixels formed on a second region of the semiconductor substrate, wherein the first region is isolated from the second region and wherein a negative voltage level is applied to the second region; and a negative voltage generator for providing the negative voltage for the second region.

Abstract translation: 本发明提供一种图像传感器，包括：第一导电类型的半导体衬底：形成在半导体衬底的第一区域上的外围电路，其中对第一区域施加接地电压电平; 具有形成在所述半导体衬底的第二区域上的多个单位像素的单位像素阵列，其中所述第一区域与所述第二区域隔离，并且其中负电压电平施加到所述第二区域; 以及用于为第二区域提供负电压的负电压发生器。

公开(公告)号：US5751653A

公开(公告)日：1998-05-12

申请号：US867455

申请日：1997-06-02

Applicant: In Sool Chung ,  Jae Jin Lee

Inventor： In Sool Chung ,  Jae Jin Lee

IPC: G11C11/407 ,  G11C11/34 ,  G11C11/406 ,  G11C11/408 ,  G11C13/00

CPC classification number: G11C11/4087 ,  G11C11/4085

Abstract: A DRAM with reduced leakage current includes at least two line driving means for transmitting high potential to a line selected by an address signal externally input; a main power line for transmitting a power source voltage externally supplied; secondary power lines for transmitting the power source voltage to the respective line driving means; switching means respectively connected between the main power line and secondary power lines; block selection means for outputting a signal where two block selection addresses are logically combined, to each of the line driving means, in order to select and operate one of the line driving means; and switching control means for outputting a signal which controls each of the switching means through the logical combination of the output signal of the block selection means and a refresh operation mode signal.

Abstract translation: 具有减小的漏电流的DRAM包括用于将高电位传输到由外部输入的地址信号选择的线路的至少两个线路驱动装置; 用于发送外部电源电压的主电力线; 用于将电源电压发送到各线路驱动装置的二次电力线路; 分别连接在主电力线和二次电力线之间的开关装置; 块选择装置，用于将两个块选择地址逻辑地组合的信号输出到每个线路驱动装置，以便选择和操作线路驱动装置之一; 以及切换控制装置，用于通过块选择装置的输出信号和刷新操作模式信号的逻辑组合输出控制每个切换装置的信号。

公开(公告)号：US5475247A

公开(公告)日：1995-12-12

申请号：US259182

申请日：1994-06-13

Applicant: Jae-Kap Kim ,  In-Sool Chung

Inventor： Jae-Kap Kim ,  In-Sool Chung

IPC: H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L21/76802 ,  H01L23/5222 ,  H01L27/10808 ,  H01L27/10873 ,  H01L2924/0002

Abstract: In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact region of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.

Abstract translation: 在动态随机存取存储器单元的制造过程中，用于防止位线和字线之间的电容耦合的导电层形成在整个存储单元的表面之外，除了位线的接触区域和存储器 电极。 此外，由于在形成接触孔的蚀刻工艺中使用用于防止电容耦合的导电层作为蚀刻阻挡层，因此形成自对准的接触。 因此，由电容耦合引起的动态随机存取存储器单元的操作受到保护，并且制造了高度集成的动态随机存取存储单元。

公开(公告)号：US5717650A

公开(公告)日：1998-02-10

申请号：US778720

申请日：1996-12-27

Applicant: In Sool Chung ,  Jae Jin Lee

Inventor： In Sool Chung ,  Jae Jin Lee

IPC: G11C11/407 ,  G11C8/10 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: Row/column decoder circuits for a semiconductor memory device. Switching elements are used to separate a main power line from the row decoder circuit to block power from the main power line to the row decoder circuit when a word line is not driven. Therefore, the amount of standby current consumption can be reduced. Also, switching elements are used to separate a main power line from the column decoder circuit to block power from the main power line to the column decoder circuit when a bit line is not selected. Therefore, the amount of standby current consumption can be reduced.

Abstract translation: 用于半导体存储器件的行/列解码器电路。 当字线不被驱动时，开关元件用于将主电源线与行解码器电路分离以阻断从主电源线到行解码器电路的电力。 因此，可以减少待机电流消耗量。 此外，当未选择位线时，开关元件用于将主电源线与列解码器电路分离，以阻断从主电源线到列解码器电路的电力。 因此，可以减少待机电流消耗量。

公开(公告)号：US5352621A

公开(公告)日：1994-10-04

申请号：US46201

申请日：1993-04-14

Applicant: Jae-Kap Kim ,  In-Sool Chung

Inventor： Jae-Kap Kim ,  In-Sool Chung

IPC: H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L21/76802 ,  H01L23/5222 ,  H01L27/10808 ,  H01L27/10873 ,  H01L2924/0002

Abstract: In the manufacturing process of a Dynamic Random Access Memory cell, the conducting layer used for preventing the capacitive coupling between a bit line and a word line is formed over the surface of the entire memory cell excepting the contact legion of a bit line and a storage electrode. Moreover, as the conducting layer used for preventing the capacitive coupling is used as an etching barrier in the etching process forming a contact hole, self-aligned contacts are formed. Therefore, the operation of the unwanted cell of a Dynamic Random Access Memory cell caused by the capacitive coupling is protected and a highly integrated Dynamic Random Access Memory cell is manufactured.

Abstract translation: 在动态随机存取存储器单元的制造过程中，用于防止位线和字线之间的电容耦合的导电层形成在整个存储单元的表面之外，除了位线和存储器的接触线之外 电极。 此外，由于在形成接触孔的蚀刻工艺中使用用于防止电容耦合的导电层作为蚀刻阻挡层，因此形成自对准的接触。 因此，由电容耦合引起的动态随机存取存储器单元的操作受到保护，并且制造了高度集成的动态随机存取存储单元。