公开(公告)号：US20080191287A1

公开(公告)日：2008-08-14

申请号：US11674660

申请日：2007-02-13

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

摘要翻译： 首先，提供具有第一有源区和第二有源区的半导体基板。 第一有源区包括第一晶体管，第二有源区包括第二晶体管。 第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。 通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。 去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

公开(公告)号：US20080176401A1

公开(公告)日：2008-07-24

申请号：US11626004

申请日：2007-01-23

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/3065

CPC分类号： H01L21/02063 ,  H01L21/76814

摘要： A method for forming a contact hole. The method comprises steps of performing a substrate having at least a dielectric layer formed thereon and then forming a patterned mask layer on the dielectric layer, wherein the patterned mask layer exposes a portion of the dielectric layer. The dielectric layer is patterned to form a contact hole by using the patterned mask layer as a mask, wherein an aspect ratio of the contact hole is larger than 4. The patterned mask layer is removed and a wet cleaning process is performed. A plasma treatment is performed on the substrate in a first tool system, wherein a gas source for the plasma treatment is a hydrogen-nitrogen-containing gas. A vacuum system of the first tool system is broken and then the substrate is transferred into a second tool system. An argon plasma treatment is performed on the substrate in the second tool system.

摘要翻译： 一种形成接触孔的方法。 该方法包括以下步骤：执行至少在其上形成介电层的衬底，然后在电介质层上形成图案化掩模层，其中图案化掩模层露出电介质层的一部分。 图案化电介质层以通过使用图案化掩模层作为掩模形成接触孔，其中接触孔的纵横比大于4.除去图案化掩模层并进行湿式清洗处理。 在第一工具系统中的基板上进行等离子体处理，其中用于等离子体处理的气体源是含氢气体。 第一工具系统的真空系统被破坏，然后将衬底转移到第二工具系统中。 在第二工具系统中的基板上进行氩等离子体处理。

公开(公告)号：US20080153295A1

公开(公告)日：2008-06-26

申请号：US12042340

申请日：2008-03-05

申请人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

发明人： Feng-Yi Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin ,  Po-Chao Tsao

IPC分类号： H01L21/768 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/76831 ,  H01L21/76897

摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.

摘要翻译： 提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。 然后对电介质层和蚀刻停止层进行构图以形成暴露半导体衬底的多个开口。 随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。 然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

公开(公告)号：US20080150041A1

公开(公告)日：2008-06-26

申请号：US12042345

申请日：2008-03-05

申请人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

公开(公告)号：US20080090422A1

公开(公告)日：2008-04-17

申请号：US11954214

申请日：2007-12-12

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/76834

摘要： An etching method is described, including a first etching step that uses a first etching gas including a first fluorinated hydrocarbon compound, and a second etching step that uses a second etching gas including a second fluorinated hydrocarbon compound. The hydrogen content in the first fluorinated hydrocarbon compound is lower than that in the second fluorinated hydrocarbon compound, such that the after-etching-inspection (AEI) critical dimension is smaller than the after-development-inspection (ADI) critical dimension.

摘要翻译： 描述了一种蚀刻方法，包括使用包括第一氟化烃化合物的第一蚀刻气体的第一蚀刻步骤和使用包括第二氟化烃化合物的第二蚀刻气体的第二蚀刻步骤。 第一氟化烃化合物中的氢含量低于第二氟化烃化合物中的氢含量，使得蚀刻后检验（AEI）临界尺寸小于显影后检验（ADI）临界尺寸。

公开(公告)号：US20080045033A1

公开(公告)日：2008-02-21

申请号：US11464496

申请日：2006-08-15

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang ,  Chuan-Kai Wang

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang ,  Chuan-Kai Wang

IPC分类号： H01L21/467 ,  H01L23/58

CPC分类号： H01L21/0271 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/32139

摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.

摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。

公开(公告)号：US20070093055A1

公开(公告)日：2007-04-26

申请号：US11163597

申请日：2005-10-24

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31116

摘要： A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer dielectric (ILD) layer on the contact etch stop layer. A photoresist pattern is formed on the ILD layer. The photoresist pattern has an opening directly above the conductive region. Using the photoresist pattern as an etch hard mask and the contact etch stop layer as an etch stop, an anisotropic dry etching process is performed to etch the ILD layer through the opening, thereby forming an upper hole region. The photoresist pattern is removed. An isotropic dry etching process is performed to dry etching the contact etch stop layer selective to the ILD layer through the upper hole region, thereby forming a widened, lower contact bottom that exposes an increased surface area of underlying conductive region.

摘要翻译： 衬底上具有由接触孔部分露出的导电区域，覆盖衬底并覆盖导电区域的接触蚀刻停止层以及接触蚀刻停止层上的层间电介质层（ILD）层。 在ILD层上形成光刻胶图形。 光致抗蚀剂图案具有直接在导电区域上方的开口。 使用光致抗蚀剂图案作为蚀刻硬掩模和接触蚀刻停止层作为蚀刻停止件，执行各向异性干蚀刻工艺以通过开口蚀刻ILD层，从而形成上部孔区域。 去除光致抗蚀剂图案。 执行各向同性干蚀刻工艺，以通过上孔区域干蚀刻对ILD层有选择性的接触蚀刻停止层，从而形成暴露下面导电区域的增加的表面积的加宽的下接触底部。

公开(公告)号：US20070051698A1

公开(公告)日：2007-03-08

申请号：US11162271

申请日：2005-09-05

申请人： Kevin CK Wang ,  Jiunn-Hsiung Liao

发明人： Kevin CK Wang ,  Jiunn-Hsiung Liao

IPC分类号： C23F1/00 ,  H01L21/302 ,  H01L21/306

CPC分类号： H01L21/0274

摘要： A photoresist trimming process is described. An etcher equipped with an etching chamber, a wafer holder, a TCP source and a TCP window is provided. After plasma is generated in the etching chamber, the etching chamber is heated without a wafer therein, and the temperature at the TCP window is monitored simultaneously. It is started, at any time after the temperature at the TCP window reaches a predetermined one, to treat wafers with photoresist layers to be trimmed thereon through the etching chamber.

摘要翻译： 描述光致抗蚀剂修剪工艺。 提供一种装备有蚀刻室，晶片保持器，TCP源和TCP窗口的蚀刻器。 在蚀刻室中产生等离子体之后，加热蚀刻室而没有晶片，并同时监视TCP窗口的温度。 在TCP窗口的温度达到预定值之后的任何时间开始，通过蚀刻室处理具有待修整的光致抗蚀剂层的晶片。

公开(公告)号：US06736146B2

公开(公告)日：2004-05-18

申请号：US09682304

申请日：2001-08-16

申请人： Jiunn-Hsiung Liao ,  Ching-Chung Chen

发明人： Jiunn-Hsiung Liao ,  Ching-Chung Chen

IPC分类号： C25F500

CPC分类号： G02B5/201 ,  Y10S134/902 ,  Y10S438/906

摘要： A method of removing non-polar colorants of a color filter array rapidly from a bottom layer starts by performing a cracking process to decompose cross-linked polymeric molecules of non-polar R/G/B colorants to smaller fragments. A plasma cleaning process is performed to oxidize the cracked non-polar R/G/B colorants. Then, a solvent cleaning process is performed by using a non-polar solvent to remove the non-polar R/G/B colorants from the bottom layer.

摘要翻译： 从底层快速除去滤色器阵列的非极性着色剂的方法开始于将非极性R / G / B着色剂的交联聚合物分子分解成较小碎片的裂解过程。 进行等离子体清洁处理以氧化破裂的非极性R / G / B着色剂。 然后，通过使用非极性溶剂从底层除去非极性R / G / B着色剂进行溶剂清洗处理。

公开(公告)号：US08633549B2

公开(公告)日：2014-01-21

申请号：US13267068

申请日：2011-10-06

申请人： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

发明人： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

IPC分类号： H01L27/11 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

摘要翻译： 半导体器件包括金属栅电极，无源器件和硬掩模层。 无源器件具有多晶硅元件层。 硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露， 第二个开口 并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。