公开(公告)号：US12271317B2

公开(公告)日：2025-04-08

申请号：US18598978

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/1009

Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

公开(公告)号：US20250113487A1

公开(公告)日：2025-04-03

申请号：US18978230

申请日：2024-12-12

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  M. Jared Barclay ,  Bhavesh Bhartia ,  Chet E. Carter ,  John D. Hopkins ,  Andrew Li ,  Haoyu Li ,  Alyssa N. Scarbrough ,  Grady S. Waldo

IPC: H10B43/27 ,  H10B41/27

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

公开(公告)号：US20250112643A1

公开(公告)日：2025-04-03

申请号：US18747696

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: H03M13/11 ,  H03M13/00

Abstract: Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

公开(公告)号：US20250112151A1

公开(公告)日：2025-04-03

申请号：US18781810

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Scott E. Sills ,  Yuichi Yokoyama

IPC: H01L23/528 ,  H01L23/532 ,  H10B12/00

Abstract: A microelectronic device includes a stack structure with tiers individually extending through an array area and into a staircase area horizontally neighboring the array area. The array area includes at least one access device. The staircase area includes a staircase structure having steps at ends of the tiers. At least some of the tiers individually include a conductive region, insulative regions, and discrete regions of semiconductor material. The conductive region includes conductive material extending through the array area and into the staircase area. The insulative regions are in both the array area and the staircase area. The discrete regions of semiconductor material are in the array area. The staircase area is substantially free of the semiconductor material. The conductive material is thicker in the staircase area than in the array area. Related electronic systems and methods of formation are also disclosed.

公开(公告)号：US20250112086A1

公开(公告)日：2025-04-03

申请号：US18980972

申请日：2024-12-13

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/20

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20250111884A1

公开(公告)日：2025-04-03

申请号：US18915265

申请日：2024-10-14

Applicant: Micron Technology, Inc.

Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Ramin Ghodsi

IPC: G11C29/42 ,  G11C15/04 ,  G11C29/12 ,  G11C29/20

Abstract: A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.

公开(公告)号：US20250110827A1

公开(公告)日：2025-04-03

申请号：US18782536

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, systems, and devices for concurrent read error handling operations are described. A system may perform a read error handling procedure in which operations may be performed concurrently or in succession. For example, a second read operation may be initiated while error control is being performed for a first read operation, or while data from the first read operation is being transferred to a controller. Further, the second read operation may be terminated based on identifying one or more errors in the data from the first read operation, such that the read error handling procedure may be terminated without finishing active processes of the read error handling procedure. Additionally, the system may be configured to perform the read error handling procedure such that a channel activation operation and a channel deactivation operation may be performed at the beginning and end of the read error handling procedure, respectively.

公开(公告)号：US20250110643A1

公开(公告)日：2025-04-03

申请号：US18747658

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F3/06

Abstract: Apparatuses, systems, and methods for bounded fault compliant metadata storage. A memory module may be capable of repairing information along a portion of the data terminals of a memory device. To prevent errors in the metadata from propagating across more than the correctable portion, the metadata may be provided along a portion of the data terminals, while the data associated with that metadata is provided along more data terminals. For example, in a 9×2p2 module the data may use two terminals, while the metadata only uses one. In a 5×2p4 module, the metadata may use a pair of terminals, while the data uses four.

公开(公告)号：US12266751B2

公开(公告)日：2025-04-01

申请号：US18535564

申请日：2023-12-11

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert

IPC: H01L33/62 ,  H01L33/06 ,  H01L33/10 ,  H01L33/14 ,  H01L33/32 ,  H01L33/36 ,  H01L33/38 ,  H01L33/40 ,  H01L33/42 ,  H01L33/44 ,  H01L33/46 ,  H01L33/60 ,  H10K50/814

Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.

公开(公告)号：US12266739B2

公开(公告)日：2025-04-01

申请号：US18401212

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert ,  Vladimir Odnoblyudov

IPC: H01L33/40 ,  H01L33/06 ,  H01L33/32 ,  H01L33/38 ,  H01L33/50 ,  H01L33/58

Abstract: Systems and methods for improved light emitting efficiency of a solid state transducer (SST), for example light emitting diodes (LED), are disclosed. One embodiment of an SST die in accordance with the technology includes a reflective material disposed over electrical connectors on a front side of the die. The reflective material has a higher reflectivity than a base material of the connectors such that light traveling toward the connectors reflects back out of the device.