公开(公告)号：US5579005A

公开(公告)日：1996-11-26

申请号：US356075

申请日：1994-12-14

申请人： Angelo Moroni

发明人： Angelo Moroni

IPC分类号： H03M1/38 ,  H03M1/06

CPC分类号： H03M1/0612 ,  H03M1/38

摘要： An analog-to-digital converter (ADC), comprising an internal digital-to-analog converter (DAC), driven by a successive approximation register (SAR), and a comparator, is provided with a correction logic circuit that controls the execution of a verifying and correcting routine at the end of each conversion routine. Master-Slave cells that compose the SAR are provided with a dedicated circuitry, responding to said correction control circuit, for confirming, incrementing or decrementing the bit stored in the cell by at least an LSB. An extremely simple routine, performed at the end of each conversion cycle, allows correction of incorrectly converted digital data because of the occurrence of missing codes in the internal DAC. The corrector does not require the use of memories and/or analog circuits and is very cost- effective and permits a greatly improved production yield of complex devices containing ADCs.

摘要翻译： 包括由逐次逼近寄存器（SAR）驱动的内部数模转换器（DAC）和比较器的模数转换器（ADC）设置有校正逻辑电路，其控制执行 每个转换程序结束时的验证和校正程序。 构成SAR的主从单元被提供有专用电路，响应于所述校正控制电路，用于确认，增加或减少存储在单元中的位至少LSB。 在每个转换周期结束时执行的非常简单的例程允许校正由于内部DAC中缺少代码的错误转换的数字数据。 校正器不需要使用存储器和/或模拟电路，并且非常成本有效，并且允许大大提高包含ADC的复杂器件的产量。

公开(公告)号：US5578956A

公开(公告)日：1996-11-26

申请号：US615729

申请日：1996-03-14

申请人： Giorgio Rossi ,  Fabio Marchioo ,  Liana Luoni ,  Franco Cocetta

发明人： Giorgio Rossi ,  Fabio Marchioo ,  Liana Luoni ,  Franco Cocetta

IPC分类号： H03G11/00 ,  H03F1/52 ,  H03G11/02 ,  H03K17/082 ,  H03K5/08

CPC分类号： H03F1/523 ,  H03K17/0822

摘要： The invention concerns a circuit for limiting the maximum current to be supplied to a load through a power MOS, being an improvement of the limiting circuitry which uses an equalizing capacitor. The addition of circuitry with a one-way current flow between a terminal of the equalizing capacitor and the gate terminal of the power MOS is effective to lower the voltage across the capacitor and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuitry which limits current flow to one direction may include a second MOS of the same type as the power MOS. In this way, any deviations of the power MOS from its designed operation, e.g. due to its manufacturing process variation and thermal drift phenomena, can also be compensated.

摘要翻译： 本发明涉及一种用于限制通过功率MOS提供给负载的最大电流的电路，其是使用均衡电容器的限制电路的改进。 在均衡电容器的端子和功率MOS的栅极端子之间添加具有单向电流的电路有效地降低电容器两端的电压并加速其充电过程，从而使预期的电流限制动作 从电路及时的一个。 限制电流流向一个方向的电路可以包括与功率MOS相同类型的第二MOS。 以这种方式，功率MOS与其设计的操作的任何偏差，例如 由于其制造工艺变化和热漂移现象，也可以补偿。

公开(公告)号：US5576990A

公开(公告)日：1996-11-19

申请号：US367538

申请日：1995-01-03

申请人： Emilio Camerlenghi ,  Giulio Casagrande

发明人： Emilio Camerlenghi ,  Giulio Casagrande

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/34

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (V.sub.PP) and having an input terminal connected to a divider (6) of said programming voltage (V.sub.PP) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（VPP）提供并具有连接到所述编程电压（VPP）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 该解决方案使得可以在存储器件的位线上具有根据存储器单元的实际长度而变化的漏极电压。

公开(公告)号：US5576646A

公开(公告)日：1996-11-19

申请号：US473533

申请日：1995-06-07

申请人： Francesco Rezzi ,  Andrea Baschirotto ,  Rinaldo Castello

发明人： Francesco Rezzi ,  Andrea Baschirotto ,  Rinaldo Castello

IPC分类号： H03F3/34 ,  H03F3/45 ,  H03H11/04 ,  H03K5/22 ,  H03K17/60

CPC分类号： H03F3/45076 ,  H03H11/0433 ,  H03F2200/261

摘要： The invention relates to a transconductor circuit with a double input and a single output, comprising two input transistors (M1, M2) whose primary conduction terminals (D1, S1, D2, S2) are respectively connected together; in this way, variations in load current and voltage can be made lower, thereby also lowering distortion from changes in their transconductance.

摘要翻译： 本发明涉及具有双输入和单输出的跨导电路，包括其一次导通端子（D1，S1，D2，S2）分别连接在一起的两个输入晶体管（M1，M2） 以这种方式，可以降低负载电流和电压的变化，从而也降低其跨导变化的变形。

公开(公告)号：US5566138A

公开(公告)日：1996-10-15

申请号：US189978

申请日：1994-02-01

申请人： Giampaolo Lombreschi ,  Massimiliano Brambilla

发明人： Giampaolo Lombreschi ,  Massimiliano Brambilla

IPC分类号： G04C3/14 ,  H02P8/02 ,  G04F5/00 ,  G04C9/00

CPC分类号： G04C3/14

摘要： An electronic circuit for controlling an analog quartz clock, particularly for installation in automobiles, has first and second counters for generating control pulses at different rates according to whether the clock is to be operated in a normal mode, or a time-setting mode. In addition, a single 11-bit counter allows "fast" or "slow" resetting of the time by a single push button.

摘要翻译： 用于控制模拟石英时钟的电子电路，特别是用于安装在汽车中的电子电路具有第一和第二计数器，用于根据时钟是以正常模式操作还是时间设定模式，以不同的速率产生控制脉冲。 此外，单个11位计数器可通过单个按钮“快速”或“慢”重置时间。

公开(公告)号：US5565787A

公开(公告)日：1996-10-15

申请号：US462517

申请日：1995-06-05

申请人： Romano Perego

发明人： Romano Perego

IPC分类号： G01R1/04 ,  H05K7/10

CPC分类号： H05K7/1023 ,  G01R1/0433

摘要： A testing contactor is provided for testing small-size semiconductor devices with large currents at high frequencies. Each semiconductor device to be tested has a plurality of leads. The testing contactor includes a plurality of first electric contact elements. A first Kelvin contact for a lead is formed of a first electric contact element in contact with the lead. The testing contactor further includes a plurality of second electric contact elements and a plurality of electric connection elements. An electric connection element in contact with the lead effectively extends the lead. A second Kelvin contact is formed of a second electric contact element and an electric connection element, the second electric contact element in contact with the electric connection element and the electric connection element in contact with the lead.

公开(公告)号：US5553017A

公开(公告)日：1996-09-03

申请号：US310836

申请日：1994-09-22

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

摘要翻译： 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US5541884A

公开(公告)日：1996-07-30

申请号：US391147

申请日：1995-02-21

申请人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.

摘要翻译： 在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到 输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。 相同的信号也阻塞地址总线上的地址放大单元。

公开(公告)号：US5541880A

公开(公告)日：1996-07-30

申请号：US411904

申请日：1995-03-28

申请人： Giovanni Campardo ,  Marco Dallabora

发明人： Giovanni Campardo ,  Marco Dallabora

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34 ,  G11C7/00 ,  G05F3/20

CPC分类号： G11C16/3445 ,  G11C16/28 ,  G11C16/344

摘要： To reduce the supply voltage of a nonvolatile memory, a read reference signal is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic of the read reference signal is composed of two portions: a first portion, ranging between the threshold value and a predetermined value, presents a slope lower than that of the characteristic of the memory cells and a second portion, as of the predetermined value of the supply voltage, presents the same slope as the characteristics of memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells so biased as to see bias voltages lower than the supply voltage.

摘要翻译： 为了降低非易失性存储器的电源电压，产生读取参考信号，其具有范围在被擦除单元的最大允许阈值和写入单元的最小允许阈值之间的参考阈值。 为了避免降低最大电源电压，读取的参考信号的特性由两部分组成：在阈值和预定值之间的范围内的第一部分呈现比存储器单元特征的斜率低的斜率， 与供电电压的预定值一样，第二部分呈现与存储器单元的特性相同的斜率。 偏移阈值，双斜率特性是通过原始单元实现的，因此，偏置电压可以看到低于电源电压的偏置电压。

公开(公告)号：US5519656A

公开(公告)日：1996-05-21

申请号：US366259

申请日：1994-12-29

申请人： Marco Maccarrone ,  Marco Olivo ,  Carla Golla ,  Silvia Padoan

发明人： Marco Maccarrone ,  Marco Olivo ,  Carla Golla ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.

摘要翻译： 一种用于编程非易失性存储单元的电压调节器，其包括在第一和第二参考电压之间供电的放大器级，并且具有连接到第一参考电压的电阻分压器的第一输入端和反馈到所述第一参考电压的输出端 通过电流镜输入，源极跟随器晶体管由输出端控制，并通过编程线与单元连接。 还提供了连接到编程线的接地的MOS晶体管和连接在电流镜与第二参考电压之间的相应的电阻路径。