-
1.发明授权Voltage regulator for non-volatile semiconductor electrically programmable memory devices 失效用于非易失性半导体电子可编程存储器件的稳压器
公开(公告)号：US5659516A
公开(公告)日：1997-08-19
申请号：US368211
申请日：1995-01-03
摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.
摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。
-
公开(公告)号：US5576990A
公开(公告)日：1996-11-19
申请号：US367538
申请日：1995-01-03
摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (V.sub.PP) and having an input terminal connected to a divider (6) of said programming voltage (V.sub.PP) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.
摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（VPP）提供并具有连接到所述编程电压（VPP）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 该解决方案使得可以在存储器件的位线上具有根据存储器单元的实际长度而变化的漏极电压。
-
3.发明授权Voltage regulator for non-volatile semiconductor electrically programmable memory devices 失效用于非易失性半导体电子可编程存储器件的稳压器
公开(公告)号：US5905677A
公开(公告)日：1999-05-18
申请号：US831046
申请日：1997-04-01
摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.
摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。
-
公开(公告)号：US20120113711A1
公开(公告)日：2012-05-10
申请号：US13353531
申请日：2012-01-19
申请人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments,
摘要翻译： 在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。 因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。 在一些实施例中，可以改善所得到的读取窗口或边缘，
-
公开(公告)号：US08116159B2
公开(公告)日：2012-02-14
申请号：US11093877
申请日：2005-03-30
申请人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
摘要翻译： 在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。 因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。 在一些实施例中，可以改善所得到的读取窗口或边缘。
-
公开(公告)号：US08098512B2
公开(公告)日：2012-01-17
申请号：US13072911
申请日：2011-03-28
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译： 可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。 在某些情况下，较高的电流可能会改善性能。 由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。
-
7.发明申请Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof 有权亚光刻接触结构，具有优化的加热器形状的相变存储单元及其制造方法公开(公告)号：US20060049391A1
公开(公告)日：2006-03-09
申请号：US11258340
申请日：2005-10-24
申请人： Giulio Casagrande , Roberto Bez , Fabio Pellizzer
发明人： Giulio Casagrande , Roberto Bez , Fabio Pellizzer
IPC分类号： H01L47/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.
摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。
-
公开(公告)号：US06627931B1
公开(公告)日：2003-09-30
申请号：US09610311
申请日：2000-07-05
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/10814 , H01L27/10885 , H01L27/11507
摘要： Presented is a memory cell integrated in a semiconductor substrate that includes a MOS device connected in series to a capacitive element. The MOS device has first and second conduction terminals, and the capacitive element has a lower electrode covered with a layer of a dielectric material and capacitively coupled to an upper electrode. The MOS device is overlaid by at least one metallization layer that is covered with at least one top insulating layer. The capacitive element is formed on the top insulating layer. The cell is unique in that the metallization layer extends only between the MOS device and the capacitive element.
摘要翻译： 提出了集成在半导体衬底中的存储单元，其包括与电容元件串联连接的MOS器件。 MOS器件具有第一和第二导电端子，并且电容元件具有被电介质材料层覆盖并且电容耦合到上电极的下电极。 MOS器件由被至少一个顶部绝缘层覆盖的至少一个金属化层覆盖。 电容元件形成在顶部绝缘层上。 该电池是唯一的，因为金属化层仅在MOS器件和电容元件之间延伸。
-
公开(公告)号：US20120287698A1
公开(公告)日：2012-11-15
申请号：US13555346
申请日：2012-07-23
申请人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read. window or margin may be improved in some embodiments.
摘要翻译： 在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。 因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。 结果阅读。 在一些实施例中可以改善窗口或边缘。
-
公开(公告)号：US07577024B2
公开(公告)日：2009-08-18
申请号：US11807125
申请日：2007-05-25
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0061 , G11C13/0064 , G11C13/0069
摘要： A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.
摘要翻译： 可以在相变存储器中的用户命令上实现流式编程模式。 在流式编程模式下，加速编程可以通过升高其用于读取和编程的电压来实现。 重复的编程操作可以在一次斜升之后流式传输，而不会在编程操作之间降低存储器单元上的电压。 这可能会节省时间。 此外，可以在编程操作之间再次读取存储器，而不一定下降。
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.019 秒)
