公开(公告)号：US20240204127A1

公开(公告)日：2024-06-20

申请号：US18540625

申请日：2023-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Antonin ZIMMER ,  Dominique GOLANSKI ,  Sebastien PLACE ,  Guillaume MARCHAND

IPC: H01L31/107 ,  H01L21/763 ,  H01L31/0288 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L21/763 ,  H01L31/0288 ,  H01L31/1804

Abstract: The present description concerns an avalanche photodiode comprising: a main PN junction adapted to being reverse-biased; and a plurality of semiconductor regions including at least: a first epitaxial semiconductor region of a first conductivity type; and a second semiconductor region of the second conductivity type, said second region being arranged to at least partially surround the first region, and comprising surfaces in contact with surfaces of said first region. The present description also concerns a method of manufacturing such a photodiode.

公开(公告)号：US20240194763A1

公开(公告)日：2024-06-13

申请号：US18523185

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Aurore CONSTANT ,  Ferdinando IUCOLANO ,  Cristina TRINGALI

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: The present disclosure relates to a HEMT transistor comprising a first semiconductor layer, a gate arranged on a first surface of the first semiconductor layer, a first passivation layer made of a first material on the sides of the gate, the first passivation layer further extending over a first portion of said surface of the first semiconductor layer, and a second passivation layer made of a second material different from the first material on a second portion of said surface of the first semiconductor layer next to the first passivation layer.

公开(公告)号：US20240194570A1

公开(公告)日：2024-06-13

申请号：US18531010

申请日：2023-12-06

Applicant: STMicroelectronics International N.V.

Inventor： Mauro MAZZOLA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49503

Abstract: A common electrically conductive substrate includes substrate portions configured to host semiconductor chips. Adjacent substrate portions have mutually facing sides with elongate sacrificial connecting bars extending between the mutually facing sides. The electrically conductive substrate is cut along a length of the elongate sacrificial connecting bars to provide singulated individual substrate portions. The elongate sacrificial connecting bars are provided with an apertured structure comprising apertures distributed along the length of the elongate sacrificial connecting bars wherein the apertures provide zones of reduced resistance to cutting.

公开(公告)号：US20240192314A1

公开(公告)日：2024-06-13

申请号：US18521570

申请日：2023-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Vikram SINGH

IPC: G01S7/35

CPC classification number: G01S7/35

Abstract: An apparatus, method, and system for efficiently storing proportional data is provided. An example apparatus may include a controller configured to determine a linear estimate based on input values provided to a first circuit and proportional output values received from the first circuit. The input values include a first input value proportional to a first output value and a second input value proportional to a second output value. Further, the linear estimate of the output values may be determined based on the first output value and a linear rate of change, wherein the linear rate of change corresponds to the change from the first input value to the second input value and the change from the first output value to the second output value. The apparatus may further comprise a memory, configured to store a storage value that represents an offset of an output value from the linear estimate.

公开(公告)号：US20240191996A1

公开(公告)日：2024-06-13

申请号：US18065557

申请日：2022-12-13

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil Sayan SAHA ,  Denis CIOCCA ,  Mahesh CHOWDHARY

IPC: G01C21/00

CPC classification number: G01C21/005

Abstract: A sensor system includes a plurality of inertial measurement units (IMU) and a control circuit. The control circuit is configured to receive sensor data from each of the inertial measurement units two alignment the timestamps of the sensor data, and to fuse the sensor data from the various IMUs. The control circuit detects whether the sensor data indicates a high degree movement or a low degree of movement and selects a high dynamic fusion process or a low dynamic fusion process based on the detected degree of movement.

公开(公告)号：US20240186679A1

公开(公告)日：2024-06-06

申请号：US18526427

申请日：2023-12-01

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  Laurent SCHWARTZ ,  Ludovic FOURNEAUD

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/31 ,  H05K1/02

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/3121 ,  H05K1/0237 ,  H01L24/16 ,  H05K2201/10098

Abstract: A waveguide has a first input/output for receiving/outputting a radio frequency (RF) wave and guiding the RF wave between the first input/output and a second input/output. An electronic integrated circuit chip is electrically connected at a front face to a metal level of a carrier substrate which includes a patch antenna. An electrically insulating embedding material surrounds the electronic chip and is disposed between the patch antenna and the first input/output of the waveguide which is at least in contact with the embedding material. The electronic chip cooperates electrically with the patch antenna so as to cause the patch antenna to transmit the RF wave to the first input/output through the embedding material. The electronic chip also processes an electrical signal from the patch antenna in response to the patch antenna receiving the radio frequency wave output by the first input/output via the embedding material.

公开(公告)号：US20240178178A1

公开(公告)日：2024-05-30

申请号：US18522909

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Francesca DE VITI ,  Damian HALICKI ,  Giovanni GRAZIOSI ,  Michele DERAI

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/24 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/25 ,  H01L25/16 ,  H01L2224/19 ,  H01L2224/24195 ,  H01L2224/2501 ,  H01L2924/1205

Abstract: An integrated circuit semiconductor dice has first and second opposed surfaces. First and second electrically conductive patterns extending at the first and second opposed surfaces provide electrical coupling to the semiconductor die. An electrical component, such as a capacitor, having a length transverse to the first and second opposed surfaces of the semiconductor die, extends bridge-like between the first and second opposed surfaces. Opposed electrical contact end terminals of the electrical component are coupled to the first and second electrically conductive patterns. The electrical component is thus electrically coupled to the semiconductor die via the first and second electrically conductive patterns at the first and second opposed surfaces.

公开(公告)号：US20240177769A1

公开(公告)日：2024-05-30

申请号：US18522547

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Promod KUMAR ,  Kedar Janardan DHORI ,  Harsh RAWAT ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C8/08

Abstract: A memory array includes memory cells arranged in rows and columns where each row includes a word line connected to memory cells of the row and each column includes a bit line connected to memory cells of the column. Each memory cell stores a bit of weight data for an in-memory computation operation. A row controller circuit coupled to the word lines through drive circuits is configured to simultaneously actuate multiple word lines during the in-memory computation operation. A column processing circuit includes a discharge time sensing circuit for each column that generates an analog signal indicative of a time taken during the in-memory computation operation to discharge the bit line from a precharge voltage to a threshold voltage. The analog signals are converted to digital signal and a computation circuitry performs digital signal processing calculations on the digital signals to generate a decision output for the in-memory computation operation.

公开(公告)号：US20240170446A1

公开(公告)日：2024-05-23

申请号：US18508071

申请日：2023-11-13

Applicant: STMicroelectronics International N.V.

Inventor： Sandrine LHOSTIS ,  Bassel AYOUB ,  Laurent FREY

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present description concerns a method of assembly of a first assembly layer comprising a first copper region at a first surface and of a second assembly layer comprising a second region made of oxide or of an oxidized metal at a second surface, wherein the first and second surfaces are assembled by means of a hybrid bonding such that the entire first copper region is placed into contact with the oxide or the oxidized metal of the second region.

公开(公告)号：US11991028B1

公开(公告)日：2024-05-21

申请号：US18059103

申请日：2022-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Iztok Bratuz ,  Vinko Kunc ,  Maksimiljan Stiglic

IPC: H04L25/49

CPC classification number: H04L25/4904

Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.