公开(公告)号：US20130132693A1

公开(公告)日：2013-05-23

申请号：US13740351

申请日：2013-01-14

申请人： Shuji KONDO ,  Katsuhiro OKUMOTO

发明人： Shuji KONDO ,  Katsuhiro OKUMOTO

IPC分类号： G06F11/14

CPC分类号： G06F11/1645 ,  G06F11/1456 ,  G06F11/2058 ,  G06F11/2074 ,  G06F11/2079 ,  G06F11/2082 ,  G06F2201/855

摘要： In a previous storage apparatus, differential JNLs are reflected in order of the sequential numbers, to the data volumes thereof. If a first storage apparatus is suspended, it is determined which is newer: the sequential number which the journal recently reflected in a second storage apparatus or the sequential number reflected in a third storage apparatus. In the newer storage apparatus having the newer sequential number, it is determined whether one or more JNLs from the journal having the sequential number next to the sequential number which is not determined to be the newer to the journal having the sequential number determined to be the newer exist, or not. If the result of the determination is positive, from the newer storage apparatus to the previous storage apparatus which is not the newer of the second and the third storage apparatuses, one or more differential JNLs are copied.

摘要翻译： 在先前的存储装置中，差分JNL以顺序号的顺序反映到其数据量。 如果第一存储装置被暂停，则确定哪个是较新的：日志最近在第二存储装置中反映的顺序号或反映在第三存储装置中的顺序号。 在具有较新序列号的较新的存储装置中，确定来自日志的一个或多个JNL是否具有连续编号的顺序号，该顺序号未被确定为具有确定为序列号的序列的日志的较新者 更新是否存在。 如果确定结果为肯定，则从新的存储装置到不是第二和第三存储装置的新的存储装置，复制一个或多个差分JNL。

公开(公告)号：US08365024B2

公开(公告)日：2013-01-29

申请号：US12713712

申请日：2010-02-26

申请人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

发明人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

IPC分类号： G01R31/28 ,  G06F7/02 ,  H03M13/00

CPC分类号： G06F11/1645 ,  G06F11/1625 ,  H04L1/244

摘要： Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

摘要翻译： 提供了用于验证跨多轨数据总线传输的信号的完整性的方法和装置。 该方法和装置提供由第一处理器和第二处理器独立地处理信号，第一和第二处理器并联连接，从而产生第一处理信号和第二处理信号。 每个经处理的信号被分成第一组分序列和第二组分序列，第一组分序列不同于第二组分序列。 然后确定第一组分序列不相同，并且第二组分序列不相同。 如果第一分量序列中的任一个不相同，或者如果第二分量序列中的任一个不相同，则通过总线的第一或第二轨道向接收设备发送错误信号。

公开(公告)号：US08065564B2

公开(公告)日：2011-11-22

申请号：US12837059

申请日：2010-07-15

申请人： Hiroshi Nakatani ,  Naoto Seto ,  Makoto Toko ,  Eigo Fukai

发明人： Hiroshi Nakatani ,  Naoto Seto ,  Makoto Toko ,  Eigo Fukai

IPC分类号： G06F11/00

CPC分类号： G06F11/1645 ,  G06F11/165 ,  G06F11/1687 ,  G06F2201/83

摘要： First and second processing units execute the same control program to the same input data in parallel. An input/output unit generates the input data and receives one of two output data executed by the first and second processing units. A channel selection unit sends the input data to the first and second processing units and sends the one to the input/output unit by selecting the one from the two output data. In the first and second processing units, a control cycle synchronization unit generates a control cycle signal at a control cycle, a processor executes the control program, a data memory stores operation data including the input data, intermediate data being executed and output data executed by the processor. A diagnostics unit generates summary information by compressing the operation data and comparatively decides whether the summary information matches the other summary information of the other processing unit every control cycle.

摘要翻译： 第一和第二处理单元对相同的输入数据并行地执行相同的控制程序。 输入/输出单元产生输入数据并接收由第一和第二处理单元执行的两个输出数据之一。 频道选择单元将输入数据发送到第一处理单元和第二处理单元，并通过从两个输出数据中选择一个，将该数据发送到输入/输出单元。 在第一和第二处理单元中，控制周期同步单元在控制周期生成控制周期信号，处理器执行控制程序，数据存储器存储包括输入数据，正在执行的中间数据和由 处理器。 诊断单元通过压缩操作数据生成概要信息，并且比较地确定概要信息是否与每个控制周期的其他处理单元的其他概要信息相匹配。

公开(公告)号：US07971095B2

公开(公告)日：2011-06-28

申请号：US11058764

申请日：2005-02-16

申请人： Richard Hess ,  Gerald B. Kelly ,  Randy Rogers ,  Kent A. Stange

发明人： Richard Hess ,  Gerald B. Kelly ,  Randy Rogers ,  Kent A. Stange

IPC分类号： G06F11/00

CPC分类号： G06F11/1438 ,  G06F11/1645 ,  G06F11/1658 ,  G06F11/1679

摘要： System and methods for providing a recoverable real time multi-tasking computer system are disclosed. In one embodiment, a system comprises a real time computing environment, wherein the real time computing environment is adapted to execute one or more applications and wherein each application is time and space partitioned. The system further comprises a fault detection system adapted to detect one or more faults affecting the real time computing environment and a fault recovery system, wherein upon the detection of a fault the fault recovery system is adapted to restore a backup set of state variables.

摘要翻译： 公开了用于提供可恢复的实时多任务计算机系统的系统和方法。 在一个实施例中，系统包括实时计算环境，其中实时计算环境适于执行一个或多个应用，并且其中每个应用程序是时间和空间分区的。 该系统还包括适于检测影响实时计算环境的一个或多个故障的故障检测系统和故障恢复系统，其中，在检测到故障时，故障恢复系统适于恢复状态变量的备份集。

公开(公告)号：US20110138230A1

公开(公告)日：2011-06-09

申请号：US12837059

申请日：2010-07-15

申请人： Hiroshi Nakatani ,  Naoto Seto ,  Makoto Toko ,  Eigo Fukai

发明人： Hiroshi Nakatani ,  Naoto Seto ,  Makoto Toko ,  Eigo Fukai

IPC分类号： G06F11/07

CPC分类号： G06F11/1645 ,  G06F11/165 ,  G06F11/1687 ,  G06F2201/83

摘要： First and second processing units execute the same control program to the same input data in parallel. An input/output unit generates the input data and receives one of two output data executed by the first and second processing units. A channel selection unit sends the input data to the first and second processing units and sends the one to the input/output unit by selecting the one from the two output data. In the first and second processing units, a control cycle synchronization unit generates a control cycle signal at a control cycle, a processor executes the control program, a data memory stores operation data including the input data, intermediate data being executed and output data executed by the processor. A diagnostics unit generates summary information by compressing the operation data and comparatively decides whether the summary information matches the other summary information of the other processing unit every control cycle.

摘要翻译： 第一和第二处理单元对相同的输入数据并行地执行相同的控制程序。 输入/输出单元产生输入数据并接收由第一和第二处理单元执行的两个输出数据之一。 频道选择单元将输入数据发送到第一处理单元和第二处理单元，并通过从两个输出数据中选择一个，将该数据发送到输入/输出单元。 在第一和第二处理单元中，控制周期同步单元在控制周期生成控制周期信号，处理器执行控制程序，数据存储器存储包括输入数据，正在执行的中间数据和由 处理器。 诊断单元通过压缩操作数据生成概要信息，并且比较地确定概要信息是否与每个控制周期的其他处理单元的其他概要信息相匹配。

公开(公告)号：US07519856B2

公开(公告)日：2009-04-14

申请号：US11311338

申请日：2005-12-20

申请人： Fumitoshi Mizutani

发明人： Fumitoshi Mizutani

IPC分类号： G06F11/00

CPC分类号： G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1683

摘要： There is provided a fault tolerant system capable of adequately performing error processing, synchronization processing, and resynchronization processing for realizing a fault tolerant function in accordance with the system state. The fault tolerant system comprises at least two systems including: a CPU subsystem; an IO subsystem connected to the CPU subsystem; an FT controller to be connected between the CPU subsystem and IO subsystem; and crosslinks connecting own system and other system through the FT controller. The CPU subsystem operates at the same timing with a CPU subsystem of other system in lock-step. The FT controller manages a plurality of system operations, according to which both systems perform error processing, duplication processing, and resynchronization processing for fault tolerant, by associating a plurality of states corresponding to the system operations with predetermined event signals. According to these event signals, the FT controller selects the system operations while changing the states for every system and allows the CPU subsystem to perform the selected system operation.

摘要翻译： 提供了能够根据系统状态适当地执行错误处理，同步处理和再同步处理以实现容错功能的容错系统。 所述容错系统包括至少两个系统，包括：CPU子系统; 连接到CPU子系统的IO子系统; 要连接在CPU子系统和IO子系统之间的FT控制器; 并通过FT控制器连接自己的系统和其他系统。 CPU子系统与其他系统的CPU子系统在锁定步骤中以相同的时序运行。 FT控制器管理多个系统操作，根据该系统操作，两个系统通过将与系统操作相对应的多个状态与预定事件信号相关联来进行容错的错误处理，复制处理和重新同步处理。 根据这些事件信号，FT控制器在改变每个系统的状态时选择系统操作，并允许CPU子系统执行所选择的系统操作。

公开(公告)号：US07194671B2

公开(公告)日：2007-03-20

申请号：US10039587

申请日：2001-12-31

申请人： Steven J. Tu ,  Alexander J. Honcharik ,  Hang T. Nguyen ,  Sujat Jamil ,  Quinn W. Merrell

发明人： Steven J. Tu ,  Alexander J. Honcharik ,  Hang T. Nguyen ,  Sujat Jamil ,  Quinn W. Merrell

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/165 ,  G06F11/1641 ,  G06F11/1645

摘要： An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.

摘要翻译： 处理器包括以FRC模式操作的第一和第二执行核心，用于比较来自第一和第二执行核心的结果的FRC检查单元和用于检测第一和第二核心中的可恢复错误的错误检查单元。 FRC检查单元临时存储来自第一或第二核的结果，并且如果检测到不匹配，则定时器被激活。 如果错误检测器在定时器间隔到期之前检测到可恢复的错误，则激活恢复例程。 如果定时器间隔首先到期，则复位例程被激活。

公开(公告)号：US20060150004A1

公开(公告)日：2006-07-06

申请号：US11311338

申请日：2005-12-20

申请人： Fumitoshi Mizutani

发明人： Fumitoshi Mizutani

IPC分类号： G06F11/00

CPC分类号： G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1683

摘要： There is provided a fault tolerant system capable of adequately performing error processing, synchronization processing, and resynchronization processing for realizing a fault tolerant function in accordance with the system state. The fault tolerant system comprises at least two systems including: a CPU subsystem; an IO subsystem connected to the CPU subsystem; an FT controller to be connected between the CPU subsystem and IO subsystem; and crosslinks connecting own system and other system through the FT controller. The CPU subsystem operates at the same timing with a CPU subsystem of other system in lock-step. The FT controller manages a plurality of system operations, according to which both systems perform error processing, duplication processing, and resynchronization processing for fault tolerant, by associating a plurality of states corresponding to the system operations with predetermined event signals. According to these event signals, the FT controller selects the system operations while changing the states for every system and allows the CPU subsystem to perform the selected system operation.

公开(公告)号：US20050246587A1

公开(公告)日：2005-11-03

申请号：US11042981

申请日：2005-01-25

申请人： David Bernick ,  William Bruckert ,  David Garcia ,  Robert Jardine ,  Pankaj Mehra ,  James Smullen

发明人： David Bernick ,  William Bruckert ,  David Garcia ,  Robert Jardine ,  Pankaj Mehra ,  James Smullen

IPC分类号： G06F9/46 ,  G06F11/00 ,  G06F11/16 ,  G06F11/18 ,  G06F12/00

CPC分类号： G06F11/1658 ,  G06F9/52 ,  G06F11/1641 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/184 ,  G06F11/185 ,  G06F11/3404 ,  G06F11/3476 ,  G06F11/3495 ,  G06F11/3636 ,  G06F11/366 ,  G06F2201/88

摘要： Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.

摘要翻译： 确定用户程序是否进行了系统级别的调用以及用户程序是否不兼容容错操作的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括从第一处理器向第二处理器提供信息（指示在第一处理器上执行的用户程序在预定时间量内没有进行系统级别调用的信息），以及 由第一处理器确定使用来自第二处理器的信息，在第二处理器中基本上同时执行的用户程序的副本是否在预定的时间量内进行了系统级的调用。

公开(公告)号：US20050223274A1

公开(公告)日：2005-10-06

申请号：US11042548

申请日：2005-01-25

申请人： David Bernick ,  William Bruckert ,  David Garcia ,  Robert Jardine ,  James Klecka ,  Pankaj Mehra ,  James Smullen

发明人： David Bernick ,  William Bruckert ,  David Garcia ,  Robert Jardine ,  James Klecka ,  Pankaj Mehra ,  James Smullen

IPC分类号： G06F11/18 ,  G06F9/52 ,  G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/16 ,  G06F15/16

CPC分类号： G06F11/1683 ,  G06F9/3851 ,  G06F9/3861 ,  G06F11/1482 ,  G06F11/1645 ,  G06F11/1691

摘要： A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.

摘要翻译： 松散锁定非确定性处理器的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括执行用户程序的容错副本，在执行非确定性执行的第一处理器中执行的用户程序的一个副本以及在第二处理器中执行的用户程序的副本 执行非确定性执行，其中在第一处理器和第二处理器中的执行不是按循环逐步锁定。