-
公开(公告)号：US20160173112A1
公开(公告)日：2016-06-16
申请号：US15050857
申请日：2016-02-23
Applicant: Cirrus Logic, Inc.
Inventor： Tejasvi Das , John L. Melanson
CPC classification number: H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
Abstract: In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
-
公开(公告)号：US09362943B2
公开(公告)日：2016-06-07
申请号：US14695385
申请日：2015-04-24
Applicant: Trigence Semiconductor, Inc.
Inventor： Akira Yasuda , Jun-ichi Okamura
Abstract: Provided is a data converter which is provided with a clock signal input part which inputs a clock signal, and an input part which inputs an input signal, a sampling part which, in response to the clock signal input to the clock signal input part, performs sampling of the input signal input to the input part, and a signal processing part which performs signal processing according to the sampling cycle and outputs an output signal, wherein when the cycle of the clock signal input to the clock signal input part becomes longer, the output signals output by the signal processing part are reduced.
Abstract translation: 提供了一种数据转换器，其设置有输入时钟信号的时钟信号输入部分和输入输入信号的输入部分，响应于输入到时钟信号输入部分的时钟信号执行的采样部分 输入到输入部的输入信号的采样，以及根据采样周期执行信号处理的信号处理部，输出输出信号，其中，当输入到时钟信号输入部的时钟信号的周期变长时， 减少由信号处理部输出的输出信号。
-
公开(公告)号：US09287888B2
公开(公告)日：2016-03-15
申请号：US14588816
申请日：2015-01-02
Applicant: Realtek Semiconductor Corp.
Inventor： Ming-Cheng Chiang , Wei-Cheng Tang
CPC classification number: H03M1/0845 , H03M1/183 , H03M1/70 , H03M3/356 , H03M3/422 , H03M3/458 , H03M3/50
Abstract: A converter with an additional DC offset includes a switch circuit, a first capacitor, a plurality of additional capacitor cells and an operational amplifier. The converter uses a first additional capacitor cell and a second additional capacitor cell having a capacitor difference with the first additional capacitor to store two charges having different polarity and magnitude with each other, and further generate an inverted DC offset according to a difference between the two charges to compensate a DC offset.
Abstract translation: 具有附加DC偏移的A转换器包括开关电路，第一电容器，多个附加电容器单元和运算放大器。 转换器使用第一附加电容器单元和具有与第一附加电容器的电容器差异的第二附加电容器单元来存储彼此具有不同极性和大小的两个电荷，并且还根据两者之间的差异产生反相DC偏移 充电以补偿DC偏移。
-
公开(公告)号：US09172393B2
公开(公告)日：2015-10-27
申请号：US14633888
申请日：2015-02-27
Applicant: Broadcom Corporation
Inventor： David Stoops , Min Gyu Kim , Vinod Jayakumar
IPC: H03M3/00
Abstract: Methods, systems, and apparatuses for converting a digital input signal to an analog output signal are disclosed. A first delta-sigma modulator receives a common mode reference signal and generates a common mode control signal. A data delta-sigma modulator receives a digital input signal and generates a modulated digital input signal. A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled together generating a first output signal and second outputs coupled together generating a second output signal. An operational amplifier receives the first and second output signals and generates the analog output signal.
Abstract translation: 公开了用于将数字输入信号转换为模拟输出信号的方法，系统和装置。 第一Δ-Σ调制器接收共模参考信号并产生共模控制信号。 数据Δ-Σ调制器接收数字输入信号并产生调制数字输入信号。 洗牌器接收调制数字输入信号和共模控制信号，并产生混洗数字输入信号。 数模转换器（DAC）具有多个三电平单元DAC元件，每个三电平单元DAC元件接收混频数字输入信号的相应部分作为第一输入信号，并接收第二和第三输入信号。 三电平单元DAC元件具有耦合在一起的第一输出产生第一输出信号和耦合在一起的第二输出产生第二输出信号。 运算放大器接收第一和第二输出信号并产生模拟输出信号。
-
公开(公告)号：US20150288374A1
公开(公告)日：2015-10-08
申请号：US14243852
申请日：2014-04-02
Applicant: Amlogic Co., Ltd.
Inventor： Jinbao Lan , Haihong Zhao , Yong Zhang , Ming Shi , Shu-Sun Yu , Chieh-Yuan Chao
CPC classification number: H03M1/0668 , H03M1/0626 , H03M1/74 , H03M3/50
Abstract: A dynamic element matching method for a multi-unit-element digital-to-analog converter having unit elements comprises several steps. An element selection probability is determined as a function of a number of the unit elements and a digital signal. Next, loop filter output signals are generated as a function of the determined element selection probability and control signals for the unit elements. Certain ones of the unit elements are selected as a function of the generated loop filter output signals. The selected certain ones of the unit elements are activated for output of the converter.
Abstract translation: 具有单元元件的多单元元件数模转换器的动态元件匹配方法包括几个步骤。 元素选择概率被确定为单位元素的数量和数字信号的函数。 接下来，循环滤波器输出信号作为确定的单元元素选择概率和控制信号的函数产生。 根据生成的环路滤波器输出信号选择某些单位元件。 选择的某些单元元件被激活以用于转换器的输出。
-
Patent Agency Ranking
公开(公告)号：US09124293B2
公开(公告)日：2015-09-01
申请号：US13914145
申请日：2013-06-10
Applicant: STMicroelectronics SA
Inventor： Didier Belot , Jean-Baptiste Begueret , Yann Deval , Dominique Dallet , André Mariano
IPC: H03M3/00
Abstract: Continuous time analog/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analog input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).
Abstract translation: 连续时间模拟/数字转换器，包括被配置为接收模拟输入信号（x（t））并且包括其斩波频率等于采样的一半的高通滤波装置（MF）的Σ-Δ调制器（MSD1） 调制器（MSD1）的量化装置（QTZ）的频率（Fs）。
-
公开(公告)号：US20150229323A1
公开(公告)日：2015-08-13
申请号：US14177519
申请日：2014-02-11
Inventor： Martin KINYUA
Abstract: A circuit includes a first digital filter H(z), a second digital filter 1 1 + H ( z ) , a third digital filter, a first and a second digital modulators, and a gain block. The first digital filter generates a first output based on a digital input and a first digital output signal. The first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. The gain block amplifies the first error output by a predetermined ratio, thereby generating a second error output. The second digital modulator generates a second output and a third error output based on the second error output. The second digital filter generates a second digital output signal based on the second output. The third filter generates the feedback error output based on the third error output.
Abstract translation: 电路包括第一数字滤波器H（z），第二数字滤波器11 + H（z），第三数字滤波器，第一和第二数字调制器以及增益块。 第一数字滤波器基于数字输入和第一数字输出信号产生第一输出。 第一数字调制器产生第一数字输出信号和基于第一输出的第一误差输出和反馈误差输出。 增益块以预定比例放大第一误差输出，从而产生第二误差输出。 第二数字调制器基于第二误差输出产生第二输出和第三误差输出。 第二数字滤波器基于第二输出产生第二数字输出信号。 第三个滤波器根据第三个错误输出产生反馈误差输出。
-
公开(公告)号：US09007248B2
公开(公告)日：2015-04-14
申请号：US14028905
申请日：2013-09-17
Applicant: Fujitsu Limited
Inventor： Kazuaki Oishi
CPC classification number: H03M3/50 , H03M3/30 , H03M7/3022
Abstract: A MASH sigma-delta modulator includes: parallel integration units in M stages configured to receive N pieces of data from a previous stage, to perform integral calculation in parallel; parallel differentiation units each configured to calculate a difference between neighboring overflows of the corresponding parallel integration unit of the integration part; and a parallel-to-serial conversion part configured to parallel-to-serial convert outputs from the differentiation part, wherein the parallel integration units receive pieces of input data in parallel, the parallel integration unit in each stage and the parallel differentiation unit in each stage perform integral calculation and differential calculation in each stage in one operation clock of a frequency 1/N times a master clock frequency, and the parallel-to-serial conversion part outputs the result of the parallel-to-serial conversion in synchronization with the master clock.
Abstract translation: MASHΣ-Δ调制器包括：M级并行整合单元，被配置为从前一级接收N条数据，并行执行积分计算; 每个差分单元被配置为计算积分部分的相应的并行积分单元的相邻溢出之间的差异; 以及并行到串行转换部分，其被配置为并行 - 串行转换来自所述微分部分的输出，其中所述并行整合单元并行地接收输入数据，每个级中的并行整合单元和每个中的并行微分单元 在主时钟频率的1 / N倍的一个操作时钟中的每个级中执行积分计算和差分计算，并行到串行转换部分将与并行到串行转换的结果同步地输出 主时钟。
-
公开(公告)号：US20150036766A1
公开(公告)日：2015-02-05
申请号：US13958088
申请日：2013-08-02
Applicant: Fahmi ELSAYED , Mohamed HELAOUI , Fadhel GHANNOUCHI , Mojtaba EBRAHIMI , Bradley John MORRIS
Inventor： Fahmi ELSAYED , Mohamed HELAOUI , Fadhel GHANNOUCHI , Mojtaba EBRAHIMI , Bradley John MORRIS
IPC: H04B1/04
CPC classification number: H04B1/0475 , H03F1/02 , H03F3/24 , H03M3/02 , H03M3/50 , H03M7/302 , H03M7/3026 , H03M7/304 , H04B1/02 , H04B2001/045
Abstract: This specification discloses a level de-multiplexed DSM based transmitter and a method for providing the same. Broadly embodiments of the present specification enable wireless transmitters that are based on multi-level de-multiplexed DSM. A three-level de-multiplexed DSM based transmitter is disclosed as an example. More generally, the use of m-level de-multiplexed DSM is also taught, the specification thereby being enabling for broader applications to a person skilled in the art. At least one of the efficiency and linearity of transmitters can be enhanced as required for specific applications by a person of skill in the art in view of this specification and the teachings of its disclosed embodiments.
Abstract translation: 本说明书公开了一种基于水平解复用DSM的发射机及其提供方法。 本说明书的广义实施例使得能够基于多级解复用DSM的无线发射机。 作为示例公开了一种基于三电平解复用DSM的发射机。 更通常地，还教导了使用m级解复用DSM，因此该说明书使得能够为本领域技术人员提供更广泛的应用。 考虑到本说明书及其公开的实施例的教导，可以根据本领域技术人员的特定应用的要求来增强发射机的效率和线性度中的至少一个。
-
公开(公告)号：US20140240154A1
公开(公告)日：2014-08-28
申请号：US14019246
申请日：2013-09-05
Applicant: Broadcom Corporation
Inventor： Min Gyu Kim , Dongtian Lu , Todd L. Brooks
IPC: H03M3/00
CPC classification number: H03M3/414 , H03M3/32 , H03M3/50 , H03M7/3022
Abstract: A multi-rate sigma delta digital-to-analog converter may include a signal input and a signal output, and multiple modulators. A first of the modulator may convert a digital input signal on the signal input to an analog output signal on the signal output. Subsequent of the multiple modulators may shape and cancel quantization noise received from a proceeding modulator. One of the modulators may operate at a higher frequency than does another of the multiple modulation loops.
Abstract translation: 多速率Σ-Δ数模转换器可以包括信号输入和信号输出以及多个调制器。 调制器中的第一个可以将信号输入上的数字输入信号转换为信号输出上的模拟输出信号。 随后的多个调制器可以形成和消除从前进的调制器接收的量化噪声。 调制器中的一个可以以比多个调制回路中的另一个更高的频率工作。
-
-
-
-
-
-
-
-
-
Search Results
418
records
(took 0.02 seconds)
