公开(公告)号：US20070033448A1

公开(公告)日：2007-02-08

申请号：US11009381

申请日：2004-12-10

Applicant: Thomas Waschura ,  Robert Verity

Inventor： Thomas Waschura ,  Robert Verity

IPC: G06F11/00

CPC classification number: H04L1/241 ,  G01R31/3171 ,  H04L1/203

Abstract: An apparatus and method for measuring errors and event occurrences in a multi-valued data stream by using a dual decision bit error rate tester is disclosed. The Bit error rate tester (BERT) includes a plurality of decision circuits operative to provide a respective bit decision output signal in response to an input signal. The bit decision output signal magnitude information of a signal under test as measured over a sample window period. A comparator circuit is coupled to each of the plurality of decision circuits, and is operative to provide an event occurrence signal in response to the bit decision output signals from each of the plurality of decision circuits. The BERT provides the ability to supply additional information and feedback about the behavior and performance of the targeted device or subsystem being tested and to perform error measurements in non-constrained data (i.e. live data).

Abstract translation: 公开了一种用于通过使用双重判决误码率测试器来测量多值数据流中的错误和事件发生的装置和方法。 比特错误率测试器（BERT）包括多个判定电路，用于响应于输入信号提供相应的比特决定输出信号。 在样本窗口周期测量的被测信号的位决定输出信号幅度信息。 比较器电路耦合到多个判定电路中的每一个，并且可操作以响应于来自多个判决电路中的每一个的位决定输出信号来提供事件发生信号。 BERT提供了提供有关正在测试的目标设备或子系统的行为和性能以及在非受限数据（即实时数据）中执行错误测量）的附加信息和反馈的能力。

公开(公告)号：US20050262402A1

公开(公告)日：2005-11-24

申请号：US10848496

申请日：2004-05-18

Applicant: Raul Ballester ,  Adriaan De Lind Van Wijngaarden ,  Ralf Dohmen ,  Bernd Dotterweich ,  Swen Wunderlich

Inventor： Raul Ballester ,  Adriaan De Lind Van Wijngaarden ,  Ralf Dohmen ,  Bernd Dotterweich ,  Swen Wunderlich

IPC: G06F11/00

CPC classification number: H04L1/241

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Abstract translation: 通过将从一组基本上不相关的位错误发生器输出的G位的第一错误模式随机分配到N位的第二错误模式中，产生用于高速数据系统的位错误模式，其中G和N是整数，G是 小于或等于N.在一个实施例中，G位错误发生器产生每位周期的G位错误模式。 每个位错误发生器以规定的位错误率运行。 分配元素随机重新排列在N位分组内的单个位周期期间产生的G位的顺序和位置。 N位组对应于可以组合错误位的N个连续的数据位。 每个位错误发生器可以由线性反馈移位寄存器或其等效物来实现。 每个线性反馈移位寄存器可以使用不同的原始多项式和不同的长度。 此外，利用来自少于所有移位寄存器级的输出来产生每个错误位。

公开(公告)号：US20040264615A1

公开(公告)日：2004-12-30

申请号：US10815604

申请日：2004-03-31

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Bruno W. Garlepp ,  Fred F. Chen

IPC: H04K001/00

CPC classification number: H04B17/29 ,  G01R31/31711 ,  G06F11/08 ,  H04B17/21 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L7/033 ,  H04L7/043 ,  H04L7/10 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03949 ,  H04L27/01

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用在采用历史数据的接收机中以减少符号间干扰（ISI）。 一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。 这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。 温度和电源电压变化。 还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。 一些实施例可以过滤错误数据以促进模式特定的边缘测试。

公开(公告)号：US06222877B1

公开(公告)日：2001-04-24

申请号：US09442878

申请日：1999-11-18

Applicant: Madabusi Govindarajan

Inventor： Madabusi Govindarajan

IPC: H04B346

CPC classification number: H04L1/20 ,  G06F11/349 ,  H04B3/46 ,  H04L1/241

Abstract: A method for performance monitoring of data transparent communication links, including a method wherein each symbol in an incoming data symbol stream is sampled at the center of each bit period to create a main line data bit stream, and concurrently sampled at a time instant displaced from the center of each bit period to create a second line data bit stream. During each bit period, the digital value of the second line data stream is compared with the digital value for the corresponding bit period in the main line. If the main line and second line digital values are the same, no error is indicated. If they are different, i.e. if, for example, the main line is bit “1” and the second line is bit zero, an error called a pseudo error is entered on a counter. The number of errors counted per number of bits or time is indicated as a pseudo error rate for each point of time displacement in the user-defined set. A pseudo error rate reference curve is independently, and previously determined and stored in a controller that indicates maximum allowable pseudo error rate data as a function of the time displacement from the center of the bit period. The values of the calculated pseudo error rate are compared with the corresponding points on the reference curve, and the deviation from the reference curve is quantified by a newly defined quantity termed a “transmission safety factor”. If this factor is below a predetermined level, an alarm/notice is activated to indicate degraded performance.

Abstract translation: 一种用于数据透明通信链路的性能监视的方法，包括一种方法，其中输入数据符号流中的每个符号在每个比特周期的中心被采样以创建主线数据比特流，并且在从时移立的时刻同时采样 每个位周期的中心创建一个第二行数据位流。 在每个位周期期间，将第二行数据流的数字值与主线中的对应位周期的数字值进行比较。 如果主线和第二行数字值相同，则不会显示错误。 如果它们不同，即，例如，如果主线是位“1”而第二行是位零，则在计数器上输入被称为伪错误的错误。 每个位数或时间计数的错误数量表示为用户定义集合中每个时间点位移的伪错误率。 伪错误率参考曲线是独立的，并且预先确定并存储在控制器中，该控制器指示作为从位周期的中心的时间位移的函数的最大允许伪错误率数据。 将计算的伪误差率的值与参考曲线上的对应点进行比较，并且通过称为“传输安全系数”的新定义量量化与参考曲线的偏差。 如果该因素低于预定水平，则激活警报/通知以指示性能下降。

公开(公告)号：US5313497A

公开(公告)日：1994-05-17

申请号：US828176

申请日：1992-01-30

Applicant: Philippe Sadot ,  Bertrand Thebault ,  Marc Darmon ,  Jacques Eudes

Inventor： Philippe Sadot ,  Bertrand Thebault ,  Marc Darmon ,  Jacques Eudes

IPC: H04B1/10 ,  H04L1/24 ,  H04L27/00

CPC classification number: H04B1/1027 ,  H04L1/241 ,  H04L1/242

Abstract: A method of detecting a disturbing signal for demodulating digital data, wherein, on the modulated signal transposed into baseband, the disturbing signal is detected by periodically inserting known signals by means of a fixed guard time delay ((R+I)T.sub.s) applied to the received signal prior to demodulation, and wherein said method includes: a step of estimating the square of the modulus of the cross-correlation of the received referenced signal and of the expected signal at a determined instant when the reference signal is assumed to be present; a step of estimating the square of the correlation of the received signal at the same instant, of multiplying by a coefficient which represents the square of the threshold for the estimated correlation coefficient, and of multiplying by the number of reference symbols used in a reference burst; and a step of comparing with each other the two quantities obtained simultaneously during the preceding two steps. The invention also relates to apparatus for implementing the method. The invention is particularly applicable to digital radio beams.

Abstract translation: 一种检测用于解调数字数据的干扰信号的方法，其中，在转置到基带中的调制信号上，通过周期性地插入已知信号来检测干扰信号，该固定保护时间延迟（（R + I）Ts）被施加到 在解调之前的接收信号，并且其中所述方法包括：当假定存在参考信号时，在确定的时刻估计接收到的参考信号和期望信号的互相关的模数的平方的步骤 ; 估计相同时刻的接收信号的相关的平方的乘法运算，乘以表示估计的相关系数的阈值的平方的系数，以及乘以参考脉冲串中使用的参考符号的数量的步骤 ; 以及在前述两个步骤中同时获得的两个量的相互比较的步骤。 本发明还涉及实现该方法的装置。 本发明特别适用于数字无线电波束。

公开(公告)号：US5187811A

公开(公告)日：1993-02-16

申请号：US896913

申请日：1992-06-11

Applicant: James C. Baker ,  Stephen N. Levine ,  Larry C. Puhl ,  Scott N. Carney

Inventor： James C. Baker ,  Stephen N. Levine ,  Larry C. Puhl ,  Scott N. Carney

IPC: H03G3/34 ,  H04L1/24

CPC classification number: H03G3/342 ,  H04L1/241

Abstract: There is provided a mechanism for error detection comprising: detecting the symmetry of error distributions over adjacent time intervals and muting of a radiotelephone in response to detected loss of substantial symmetry, unless errors are attributable to valid alternative detections. It is further characterized by: detecting the symmetry of error distributions over adjacent time intervals and muting a radiotelephone as a corrective response to detected consequential asymmetry or loss of substantial symmetry (unless errors are attributable to alternative detections of valid synchronization words) and cancelling any such corrective response upon subsequent alternative detections of valid synchronization words.

Abstract translation: 提供了一种用于错误检测的机制，包括：响应于检测到的实质对称的损失，在相邻时间间隔上检测误差分布的对称性和无线电话的静音，除非错误归因于有效的替代检测。 其进一步的特征在于：检测相邻时间间隔上的误差分布的对称性，并且将无线电话机作为对检测到的相应不对称性或实质对称性的丢失的校正响应静音（除非错误归因于有效同步字的替代检测）并且取消任何这样的 对有效同步字的后续可选检测的纠正响应。

公开(公告)号：US4733395A

公开(公告)日：1988-03-22

申请号：US852336

申请日：1986-04-15

Applicant: Hans-Joachim Gelbrich ,  Erwin Lehmann

Inventor： Hans-Joachim Gelbrich ,  Erwin Lehmann

IPC: G01R31/3181 ,  G06F7/58 ,  H04L1/24 ,  G01R31/28

CPC classification number: G01R31/31813 ,  G06F7/582 ,  H04L1/241 ,  H04L1/242

Abstract: For imitating periodic signals occurring in digital transmission systems during some operating conditions in view of the multiplex structure a word generator is proposed which includes a read-only memory from which during a test signal cycle only 4116 permutations are successively read out of a total of 65,536 possible word sizes and permutations of e.g. a 16-bit word. The remaining 61,420 permutations are generated by shifting bit-by-bit the entire packet of continuous signals so that in case of a fixed 16 bit pattern the packet starts at a different bit position during each successive cycle and after 16 cycles all 16 bit positions occur as begin state. The shift is caused by a framing bit sequence which determines the test signal cycle and whose length is aliquant to n=16.

Abstract translation: 为了模拟在数字传输系统中发生在某些操作条件下的周期性信号，鉴于多路复用结构，提出了一种字生成器，其包括只读存储器，在测试信号周期期间，只有4116个排列从总共65,536个连续地读出 可能的字大小和排列例如 一个16位字。 剩余的61,420个排列是通过逐位逐位移动连续信号的整个分组而产生的，使得在固定的16位模式的情况下，分组在每个连续周期期间在不同的位位置开始，并且在16个周期之后，所有16位位置发生 作为开始状态。 移位是由确定测试信号周期并且长度等于n = 16的成帧位序列引起的。

公开(公告)号：US4580263A

公开(公告)日：1986-04-01

申请号：US544192

申请日：1983-10-21

Applicant: Tatsuo Watanabe ,  Toshio Mizuno ,  Makoto Miyake ,  Tadashi Fujino

Inventor： Tatsuo Watanabe ,  Toshio Mizuno ,  Makoto Miyake ,  Tadashi Fujino

IPC: H04L1/00 ,  H04L1/24 ,  H04L25/02 ,  G06F11/00

CPC classification number: H04L1/241

Abstract: The error rate of a signal is monitored by sampling an input signal with a first clock and also with second and third clocks phase delayed in equal but opposite directions with respect to the first clock, and then logically combining the first through third sampled outputs in order to obtain an error signal.

Abstract translation: 通过用第一时钟采样输入信号以及相对于第一时钟以相等但相反的方向相位延迟的第二和第三时钟来监视信号的误码率，然后按顺序逻辑地组合第一至第三采样输出 以获得错误信号。

公开(公告)号：US4428076A

公开(公告)日：1984-01-24

申请号：US330719

申请日：1981-12-14

Applicant: Eberhard Schuon

Inventor： Eberhard Schuon

IPC: H04L1/24 ,  H04L25/04 ,  H04B17/00 ,  H04L1/00

CPC classification number: H04L1/242 ,  H04L1/241

Abstract: In order to evaluate the fidelity of a transmission line or other test object, a pseudorandom bit pattern is fed to the input end of that test object and is compared bit by bit with the pattern exiting at its output end. Since independent transmission errors are considered particularly relevant for this evaluation, in contrast to consequential errors following an initial error within a predetermined number of bit cycles, an error pulse emitted by the bit comparator causes the blocking of further error pulses for a selected time interval. The blocking may be effected by a retriggerable monoflop of adjustable off-normal period or by a presettable down counter.

Abstract translation: 为了评估传输线或其他测试对象的保真度，将伪随机位模式馈送到该测试对象的输入端，并将其逐位与在其输出端退出的模式进行比较。 由于独立传输错误被认为与该评估特别相关，与预定数量的位周期内的初始误差之后的后果误差相反，比特比较器发出的误差脉冲导致在所选择的时间间隔内阻塞进一步的误差脉冲。 可以通过可调节的非正常时段的可再触发单声道或通过可预置的向下计数器来实现阻挡。

公开(公告)号：US4327356A

公开(公告)日：1982-04-27

申请号：US49502

申请日：1979-06-19

Applicant: John D. Gilliland

Inventor： John D. Gilliland

IPC: H04L1/24 ,  H04Q9/00 ,  H04J3/14

CPC classification number: H04L1/241

Abstract: A monitor for monitoring the performance of a digital transmission system has three level sensors for sensing at decision instants the level of a signal derived from a transmitted signal. A first of the level sensors has its threshold set at a level corresponding substantially to the eye diagram amplitude, a second has its threshold set near the upper level of the eye diagram amplitude, and the third has its threshold set near the lower level of the eye diagram amplitude. The outputs from the level sensors are connected to logic circuitry which is arranged to energize an alarm whenever the upper or lower eye amplitude level is between the thresholds of the second and third level sensors.

Abstract translation: 用于监测数字传输系统的性能的监视器具有三个级别的传感器，用于在判定时刻感测从发射信号导出的信号的电平。 水平传感器中的第一个具有其阈值设置在基本上与眼图幅度相对应的水平，第二水平传感器的阈值设置在眼图幅度幅度的上限附近，并且第三阈值设置在靠近眼图幅度的较低水平 眼图幅度。 来自电平传感器的输出连接到逻辑电路，其逻辑电路被布置成每当上眼睛或下眼睛的振幅水平在第二和第三水平传感器的阈值之间时，都会激励报警。