公开(公告)号：US20030210684A1

公开(公告)日：2003-11-13

申请号：US10422968

申请日：2003-04-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Jiin Lai ,  Patrick Lin

IPC: H04Q011/00

CPC classification number: H04L49/103 ,  H04L49/3009

Abstract: This invention is an implementation of a host channel adapter and method for transferring packet data over a network. When packets are distributed by a packet-switching system, a control unit and a plurality of header buffers allow the packet transmission to be carried out efficiently in executing the actions of reading and moving the packets. This reduces repetitions in reading and moving the packets, which enables the host channel adapter to use the bandwidth of the memory efficiently through the help of the control unit.

Abstract translation: 本发明是用于通过网络传送分组数据的主机通道适配器和方法的实现。 当分组由分组交换系统分发时，控制单元和多个报头缓冲器允许在执行读取和移动分组的动作时有效地执行分组传输。 这减少了读取和移动数据包的重复，这使得主机通道适配器能够通过控制单元的帮助有效地使用存储器的带宽。

公开(公告)号：US20030189924A1

公开(公告)日：2003-10-09

申请号：US10418280

申请日：2003-04-18

Applicant: Broadcom Corporation

Inventor： Shiri Kadambi ,  Shekhar Ambe

IPC: H04L012/66

CPC classification number: H04L12/5601 ,  H04L12/18 ,  H04L12/42 ,  H04L12/46 ,  H04L12/4625 ,  H04L12/4641 ,  H04L12/4645 ,  H04L12/467 ,  H04L12/56 ,  H04L12/5602 ,  H04L29/06 ,  H04L45/00 ,  H04L45/24 ,  H04L45/245 ,  H04L45/742 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/50 ,  H04L47/522 ,  H04L47/525 ,  H04L47/6205 ,  H04L47/6215 ,  H04L47/6225 ,  H04L47/623 ,  H04L49/102 ,  H04L49/103 ,  H04L49/107 ,  H04L49/108 ,  H04L49/109 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3036 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/602 ,  H04L49/606 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9057 ,  H04L49/9073 ,  H04L67/10 ,  H04L69/14 ,  H04L69/16 ,  H04L69/161 ,  H04L69/323 ,  H04L69/329 ,  H04L2012/5651 ,  H04L2012/5665 ,  H04L2012/5667 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5682 ,  H04L2012/5683 ,  Y02D50/30 ,  Y10S707/99931 ,  Y10S707/99945

Abstract: A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. A plurality of semiconductor-implemented lookup tables are provided, with the lookup tables including an address resolution lookup/layer three lookup, rules tables, and VLAN tables. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses. An update to an address table associated with an initial data port interface of the first and second data port interfaces results in the initial data port interface sending a synchronization signal to the other address resolution tables in the network switch. As a result, all address resolution tables on the network switch are synchronized on a per entry basis.

公开(公告)号：US06628653B1

公开(公告)日：2003-09-30

申请号：US09090285

申请日：1998-06-04

Applicant: Jamal Hadi Salim

Inventor： Jamal Hadi Salim

IPC: H04L1256

CPC classification number: H04L61/00 ,  H04L29/12009 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/351 ,  H04L69/22

Abstract: A packet processing apparatus comprises a programmable hardware discriminator for receiving incoming packets, and selecting bits from any part of the incoming packets, a decision table for storing information relating to how the packets are to be processed, programmable hardware searching logic for accessing the information in the table according to the selected bits, and a packet handler for processing the packets according to the result of the access. Since many networking processing tasks can be broken down into bit selection and table searching, this generic type of arrangement will suit a wide variety of applications. It facilitates developing logic directly in hardware which can reduce the effort needed to convert a working prototype into a product ready for use in the field, e.g. for handling new protocol components.

Abstract translation: 分组处理装置包括用于接收输入分组的可编程硬件鉴别器，以及从输入分组的任何部分选择比特，用于存储与如何处理分组有关的信息的决策表，用于访问信息中的信息的可编程硬件搜索逻辑 根据所选择的比特的表，以及根据访问结果处理分组的分组处理程序。 由于许多网络处理任务可以分解成比特选择和表搜索，这种通用类型的安排将适用于各种各样的应用。 它有助于直接在硬件中开发逻辑，这可以减少将工作原型转换为准备在现场使用的产品所需的工作，例如。 用于处理新的协议组件。

公开(公告)号：US06628613B1

公开(公告)日：2003-09-30

申请号：US09417168

申请日：1999-10-12

Applicant: Jinoo Joung ,  Young-Il Kim

Inventor： Jinoo Joung ,  Young-Il Kim

IPC: H04J302

CPC classification number: H04L47/10 ,  H04L47/30 ,  H04L49/103 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/50

Abstract: A flow control method in an Ethernet switch being a downstream device using a full duplex mode in a packet switched network of the type having a plurality of input ports connected to a plurality of Ethernet switches being upstream devices and a common memory for storing packet data received from each input port and for transmitting packet data read from the common memory to a destination upstream device. In such flow control method, the buffer state of the common memory is first determined. If the buffer state is buffer-full, a pause frame including a predetermined pause time is transmitted to the plurality of Ethernet switches being upstream devices and an expected pause time of the upstream devices is counted. The buffer state of the common memory is determined again if the expected pause time expires. If the buffer state is buffer-full, the pause frame including the predetermined pause time is re-transmitted to the plurality of Ethernet switches being upstream devices and the expected pause time of the upstream devices is initiated.

Abstract translation: 以太网交换机中的流控制方法是在具有连接到作为上游设备的多个以太网交换机的多个输入端口的类型的分组交换网络中使用全双工模式的下游设备和用于存储接收的分组数据的公共存储器 并从用于从公用存储器读取的分组数据发送到目的地上游设备。 在这种流量控制方法中，首先确定公共存储器的缓冲状态。 如果缓冲器状态为缓冲器满，则将包括预定暂停时间的暂停帧发送到作为上游设备的多个以太网交换机，并且对上游设备的预期暂停时间进行计数。 如果预期的暂停时间到期，则再次确定公共存储器的缓冲状态。 如果缓冲区状态为缓冲区满，则将包含预定暂停时间的暂停帧重新发送到作为上游设备的多个以太网交换机，并且启动上游设备的预期暂停时间。

公开(公告)号：US20030174708A1

公开(公告)日：2003-09-18

申请号：US10247568

申请日：2002-09-20

Inventor： Kizito Gysbertus Antonius Van Asten ,  Faisal Dada ,  Edward Aung Kyi Maung

IPC: H04L012/56

CPC classification number: H04L49/3027 ,  H04L12/5601 ,  H04L49/103 ,  H04L49/30 ,  H04L49/3081 ,  H04L49/505 ,  H04L49/90 ,  H04L2012/5652 ,  H04L2012/5667 ,  H04L2012/5681

Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into nullX/Nnull groups of cells; a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; and the MCP address being the same as the group address. Corresponding methods for storing and retrieving cells, single cell packets, segmented variable size packets in such memory are also provided.

Abstract translation: 提供了一种高速存储器，该存储器具有写入端口和读取端口，并且包括以下部件：多个N个存储器模块，用于存储固定大小的单元，其是被划分为X个单元的可变大小的分组的段， X细胞分为┌X/N┐组细胞; 读写控制块包括用于从写入端口接收单元并将属于同一组的每个单元存储在相同存储器地址（组地址）的N个存储器模块中选定的不同的一个中的单元的装置; 一个多小区指针（MCP）存储器，用于在MCP地址处存储用于所述一组小区（相关联的MCP）的MCP，该MCP具有N个存储器模块标识符，用于记录所述小区单元的存储单元的顺序 N个内存模块; MCP地址与组地址相同。 还提供了用于在这种存储器中存储和检索单元，单个单元包，分段可变大小分组的相应方法。

公开(公告)号：US20030174699A1

公开(公告)日：2003-09-18

申请号：US10194277

申请日：2002-07-15

Inventor： Kizito Gysbertus Antonius Van Asten ,  Faisal Dada ,  Edward Aung Kyi Maung

IPC: H04L012/28 ,  H04L012/56

CPC classification number: H04L12/5601 ,  H04L49/103 ,  H04L49/30 ,  H04L49/3027 ,  H04L49/3081 ,  H04L49/505 ,  H04L49/90 ,  H04L2012/5652 ,  H04L2012/5667 ,  H04L2012/5681

Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into nullX/Nnull groups of cells; a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; and the MCP address being the same as the group address. Corresponding methods for storing cells and/or storing and retrieving variable size packet in such memory are also provided.

Abstract translation: 提供了一种高速分组存储器，该存储器具有写入端口和读取端口，并且包括以下部件：用于存储固定大小的单元的多个N个存储器模块，它们是划分为X个单元的可变大小分组的段， X细胞分组为┌X/N┐细胞组; 读写控制块包括用于从写入端口接收单元并将属于同一组的每个单元存储在相同存储器地址（组地址）的N个存储器模块中选定的不同的一个中的单元的装置; 一个多小区指针（MCP）存储器，用于在MCP地址处存储用于所述一组小区（相关联的MCP）的MCP，该MCP具有N个存储器模块标识符，用于记录所述小区单元的存储单元的顺序 N个内存模块; MCP地址与组地址相同。 还提供了用于在这种存储器中存储单元和/或存储和检索可变大小分组的相应方法。

公开(公告)号：US20030152091A1

公开(公告)日：2003-08-14

申请号：US10357534

申请日：2003-02-03

Applicant: International Business Machines Corporation

Inventor： Mitch Gusat ,  Ferdinand Gramsamer ,  Mark Verhappen ,  Antonius Engbersen ,  Ronald P. Luijten ,  Francois G. Abel ,  Cyriel Minkenberg ,  Jose Duato

IPC: H04L012/26 ,  H04L012/56

CPC classification number: H04L47/10 ,  H04L47/30 ,  H04L47/39 ,  H04L49/103 ,  H04L49/3045

Abstract: The present invention discloses a scalable flow-control mechanism. In accordance with the present invention, there is provided a switching device for transporting packets of data, the packets being received at the switching device based on flow-control information, the device comprising a memory for storing the packets, a credit counter coupled to the memory for counting a credit number of packets departing from the memory, and a scheduler unit coupled to the credit counter for deriving the flow-control information in response to the credit number. Moreover, a switching apparatus and a method for generating flow-control information is disclosed.

Abstract translation: 本发明公开了一种可扩展的流量控制机制。 根据本发明，提供了一种用于传输数据分组的切换装置，所述数据分组基于流控制信息在交换装置处接收，所述装置包括用于存储分组的存储器，耦合到所述分组的信用计数器 用于计数从存储器离开的数据包的信用数量的存储器，以及耦合到信用计数器的调度器单元，用于响应于信用号码导出流量控制信息。 此外，公开了一种用于产生流量控制信息的开关装置和方法。

公开(公告)号：US06606326B1

公开(公告)日：2003-08-12

申请号：US09347161

申请日：1999-07-02

Applicant: Jay R. Herring

Inventor： Jay R. Herring

IPC: H04L1228

CPC classification number: H04L45/34 ,  H04L49/103 ,  H04L49/1515 ,  H04L49/90

Abstract: A central queue-based packet switch contains multiple input ports and multiple output ports coupled by a central queue path and a bypass path. The central queue has only shared memory and processing dynamically switches from transfer of message portions across the central queue path to the bypass path whenever a next message portion is identified by an output port as a critical portion. Upon transfer of message forwarding to the bypass path, subsequent message portions are forwarded across the bypass path unless the output port signals for transfer of the message portions back through the central queue path. Dynamic switching of message transfer from the central queue path to the bypass path is accomplished irrespective of whether contention exists for the output port.

Abstract translation: 基于中心队列的分组交换机包含多个输入端口和多个输出端口，它们通过中央队列路径和旁路路径耦合。 只要共享内存和处理动态地切换从消息部分跨中央队列路径传输到旁路路径，每当下一个消息部分被输出端口标识为关键部分。 在将消息转发传送到旁路路径时，后续消息部分跨越旁路路径转发，除非输出端口用于将消息部分传送回中央队列路径。 完成从中央队列路径到旁路路径的消息传输的动态切换，而不管输出端口是否存在争用。

公开(公告)号：US20030123387A1

公开(公告)日：2003-07-03

申请号：US10029879

申请日：2001-12-31

Inventor： Andrew Lloyd Jackson

IPC: H04L012/26

CPC classification number: H04L45/00 ,  H04L12/4625 ,  H04L45/60 ,  H04L49/103 ,  H04L49/351

Abstract: A device and method for filtering network traffic is provided utilizing multiple filter tables. A first filter table is maintained in the form of a balanced binary tree that is manipulated by two processors in order to filter traffic between network segments. By initially filtering traffic based upon information contained within the balanced binary tree table, the processing and resource load on the system is significantly reduced. Traffic whose source or destination is not contained within the balanced binary tree table is forwarded to a second processor for filtering based upon a second filter table.

Abstract translation: 利用多个过滤表提供一种过滤网络流量的设备和方法。 以平衡二叉树的形式维护第一过滤表，由两个处理器操纵，以过滤网段之间的流量。 通过基于平衡二叉树表中包含的信息初始地过滤业务，系统上的处理和资源负载显着减少。 其源或目的地不包含在平衡二叉树表内的流量被转发到第二处理器，用于基于第二滤波器表进行滤波。

公开(公告)号：US20030110305A1

公开(公告)日：2003-06-12

申请号：US10014007

申请日：2001-12-10

Inventor： Rahul Saxena

IPC: G06F015/16 ,  G06F015/173

CPC classification number: H04L49/351 ,  H04L49/103 ,  H04L49/90

Abstract: A switch and a process of operating a switch are described where a received data frame is stored into memory in a systematic way. In other words, a location is selected in the memory to store the received data frame using a non-random method. By storing the received data frame in this way, switches that employ this system and method increase bandwidth by avoiding delays incurred in randomly guessing at vacant spaces in the memory. The received data frame is stored until a port that is to transmit the received data frame is available. Throughput is further improved by allowing the received data frames to be stored in either contiguous or non-contiguous memory locations.

Abstract translation: 描述开关和操作开关的过程，其中接收的数据帧以系统的方式存储到存储器中。 换句话说，在存储器中选择一个位置以使用非随机方法存储所接收的数据帧。 通过以这种方式存储接收到的数据帧，采用该系统和方法的交换机通过避免在存储器空闲空间中随机猜测的延迟而增加带宽。 存储接收到的数据帧直到发送接收到的数据帧的端口可用。 通过允许所接收的数据帧存储在连续的或不连续的存储单元中来进一步提高吞吐量。