公开(公告)号：US10340406B2

公开(公告)日：2019-07-02

申请号：US15785411

申请日：2017-10-16

Applicant: Purdue Research Foundation

Inventor： Byunghoo Jung ,  Bongchan Kim

IPC: H03H15/02 ,  H01L31/08 ,  H01L27/144 ,  H01L31/101

Abstract: A distributed photodiode with FIR filtering function enabled by a lumped transmission line is provided. The distributed photodiode includes inductors, a plurality of photodiode segments, photodiode biasing components, and termination impedance. The electrical bandwidth due to the junction parasitic capacitance of the photodiode is increased as the parasitic capacitance is absorbed in the transmission line structure. Moreover, the delay elements inherent in the transmission line enable implementation of an analog finite impulse response (FIR) filter that has equalization capability to allow a customized photodiode frequency response compensation.

公开(公告)号：US10069483B1

公开(公告)日：2018-09-04

申请号：US15680987

申请日：2017-08-18

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ramin Zanbaghi ,  Siladitya Dey ,  Daniel J. Allen ,  John L. Melanson ,  Aniruddha Satoskar

IPC: H03H19/00 ,  H03H15/02 ,  H03H17/02 ,  H04B1/26 ,  H03M1/12 ,  H03H11/04 ,  H03M1/06

Abstract: A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

公开(公告)号：US09312831B2

公开(公告)日：2016-04-12

申请号：US14043009

申请日：2013-10-01

Applicant: Analog Devices, Inc.

Inventor： Eric Nestler ,  Vladimir Zlatkovic ,  Jeffrey Venuti

IPC: H03B1/00 ,  H03K5/00 ,  H04B1/10 ,  H03H7/01 ,  H03H15/02 ,  H03H15/00 ,  H03M1/12 ,  G06F17/50 ,  G10K15/00 ,  H02M1/14 ,  H04R25/00

CPC classification number: H03H7/0138 ,  G06F17/5063 ,  G10K15/00 ,  H02M1/14 ,  H03H15/00 ,  H03H15/02 ,  H03M1/12 ,  H04R25/00

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

公开(公告)号：US20050015419A1

公开(公告)日：2005-01-20

申请号：US10619771

申请日：2003-07-14

Applicant: Chiang Pu ,  Scott Chiu ,  Yonghui Tang

Inventor： Chiang Pu ,  Scott Chiu ,  Yonghui Tang

IPC: G06F17/10 ,  H03H15/02

CPC classification number: H03H15/02 ,  H03H2015/007

Abstract: Briefly, a finite impulse response filter to generating coefficients having a programmable magnitude and quantum tunability.

Abstract translation: 简而言之，有限脉冲响应滤波器用于产生具有可编程幅度和量子可调性的系数。

公开(公告)号：US6150901A

公开(公告)日：2000-11-21

申请号：US197166

申请日：1998-11-20

Applicant: Floyd Van Auken

Inventor： Floyd Van Auken

IPC: H03H7/12 ,  H03H15/02 ,  H03H9/46

CPC classification number: H03H7/12 ,  H01G5/40 ,  H03H15/02

Abstract: A programmable high frequency (HF) bandpass filter is disclosed. The programmable filter has a tunable bandwidth and center frequency over a large range of the radio frequency (RF) and intermediate frequency (IF) spectrum. The programmable filter incorporates micro-electro-mechanical switches (MEMS), Acoustic Charge Transport (ACT) devices, or a combination thereof, to provide tunability of the bandpass filter response characteristics.

Abstract translation: 公开了一种可编程高频（HF）带通滤波器。 可编程滤波器在射频（RF）和中频（IF）频谱的大范围内具有可调谐带宽和中心频率。 可编程滤波器包括微机电开关（MEMS），声电荷传输（ACT）器件或其组合，以提供带通滤波器响应特性的可调性。

公开(公告)号：US5953480A

公开(公告)日：1999-09-14

申请号：US678216

申请日：1996-07-11

Applicant: Cord-Heinrich Bartels ,  Thomas Suwald ,  Sonke Struck ,  Jorg Wolber

Inventor： Cord-Heinrich Bartels ,  Thomas Suwald ,  Sonke Struck ,  Jorg Wolber

IPC: H04N9/84 ,  H03H15/02 ,  H03H19/00 ,  H04N5/93 ,  H04N9/79 ,  H04N9/78

CPC classification number: H03H15/02 ,  H04N5/93

Abstract: A comb filter arrangement comprising at least one delay circuit and an adder, this adder being twice supplied with a video signal modulated on a carrier, which video signals are applied mutually shifted with time. The signals are delayed by the delay circuits, so that either video signal applied to the adder is delayed relative to the other video signal by a given period of time. Furthermore, the delay circuits are arranged in switched capacitor technique.

Abstract translation: 一种包括至少一个延迟电路和加法器的梳状滤波器装置，该加法器被两次提供在载波上调制的视频信号，这些视频信号被施加相互随时间移位。 信号由延迟电路延迟，使得施加到加法器的任一视频信号相对于另一个视频信号延迟给定的时间段。 此外，延迟电路以开关电容器技术布置。

公开(公告)号：US5867526A

公开(公告)日：1999-02-02

申请号：US997848

申请日：1997-12-24

Applicant: Yasuo Nagazumi

Inventor： Yasuo Nagazumi

IPC: H03H15/02 ,  H04B1/707

CPC classification number: H03H15/02

Abstract: A charge mode operation circuit dedicated to detect the correlation between analog input signal and digital code, and for realizing by "RAKE method" the path diversity reception from the correlation data obtained using the same. The circuit utilizes an analog shift register using at least one charge transfer device for transferring a charge signal packet, a plurality of charge signal generation units, arranged along the analog shift register and provided, respectively, with substantially uniform voltage charge conversion characteristic controlled by a common input sign; and a routing mechanism for selectively transferring output charge packets generated by the plurality of charge signal generation units in given directions according to digital bit signal provided separately.

Abstract translation: 一种专用于检测模拟输入信号和数字码之间的相关性的充电模式运行电路，并且用于通过“RAKE方法”从使用其获得的相关数据实现路径分集接收。 该电路使用至少一个电荷转移装置的模拟移位寄存器，用于传送沿着模拟移位寄存器布置的充电信号分组，多个充电信号产生单元，并分别提供基本均匀的电压电荷转换特性， 常用输入符号 以及路由机制，用于根据单独提供的数字比特信号，在给定方向上选择性地传送由多个计费信号产生单元产生的输出电荷分组。

公开(公告)号：US5850357A

公开(公告)日：1998-12-15

申请号：US737780

申请日：1996-11-25

Applicant: Mordechai Shefer

Inventor： Mordechai Shefer

IPC: H03H15/02 ,  G06G7/02

CPC classification number: H03H15/02

Abstract: A real time equalizer-enhancer apparatus, comprises: a plurality of analog multipliers (33) having one input (X) connected to the sampled input signal, and the other (Y) input connected to the output of an operational amplifier (34); at least one operational amplifier provided with feedback resistor (35), the output of which is connected to the input of one or more of the said plurality of analog multipliers, and the input of which is connected to one or more summing resistor, and a plurality of summing resistor; (36) connected between the output of each of the said analog multipliers (33) and the input of the operational amplifier (34); means being provided to combine the outputs of the said plurality of analog multipliers according to a predetermined combination rule, means also being provided to subtract said combination of multipliers outputs from prescribed constant bias values, and to feed the results back into the inputs of the analog multipliers (33).

Abstract translation: PCT No.PCT / US95 / 06780 Sec。 371日期：1996年11月25日 102（e）日期1996年11月25日PCT提交1995年5月26日PCT公布。 公开号WO95 / 33306 日期1995年12月7日实时均衡器增强器装置包括：具有连接到采样输入信号的一个输入（X）的多个模拟乘法器（33），以及连接到操作的输出的另一个（Y）输入 放大器（34）; 设置有反馈电阻器（35）的至少一个运算放大器，其输出连接到所述多个模拟乘法器中的一个或多个的输入端，并且其输入端连接到一个或多个求和电阻器，以及 多个求和电阻; （36），连接在所述模拟乘法器（33）中的每一个的输出端和运算放大器（34）的输入端之间; 提供用于根据预定组合规则组合所述多个模拟乘法器的输出的装置，还提供用于从规定的常数偏差值中减去乘法器输出的所述组合的装置，并将结果反馈到模拟 乘数（33）。

公开(公告)号：US4922509A

公开(公告)日：1990-05-01

申请号：US212386

申请日：1988-06-27

Applicant: Alain Tresset ,  Francois Fontenelle ,  Gerard Javard

Inventor： Alain Tresset ,  Francois Fontenelle ,  Gerard Javard

IPC: H03H15/02

CPC classification number: H03H15/02

Abstract: The invention relates to a method of implementing programmable tuned filters, in particular for telegraph signal receivers, and also to tuned filters obtained by the method. A resonator (16) organized around a multipath filter and controlled by a first clock signal is associated with a comb filter (17) organized around a delay line (21) and controlled by a second clock signal, in order to constitute a tuned filter which is programmed by the clock signals. The invention is applicable to making programmable tuned filters and banks of such filters, in particular for remote protection equipment in grids for transporting electrical power.

Abstract translation: 本发明涉及一种实现可编程调谐滤波器，特别是用于电报信号接收器的方法，以及通过该方法获得的调谐滤波器。 围绕多径滤波器组合并被第一时钟信号控制的谐振器（16）与围绕延迟线（21）组织并由第二时钟信号控制的梳状滤波器（17）相关联，以构成调谐滤波器 由时钟信号编程。 本发明可应用于制造可编程调谐滤波器和这种滤波器组，特别是用于传输电力的网格中的远程保护设备。

公开(公告)号：US4803706A

公开(公告)日：1989-02-07

申请号：US71682

申请日：1987-07-09

Applicant: Jin Murayama ,  Takashi Miida ,  Ryuji Kondo

Inventor： Jin Murayama ,  Takashi Miida ,  Ryuji Kondo

IPC: H01L21/339 ,  G11C19/00 ,  G11C19/28 ,  H01L29/762 ,  H03H15/02 ,  H01L29/78

CPC classification number: G11C19/282 ,  G11C19/00

Abstract: A various CCD delay element in which extra delay stages are provided. The extra stages are either held at a given potential to pass all signals therethrough and thus to not contribute to the gain or are connected to the clock signals to thereby increase the delay.

Abstract translation: 提供额外的延迟级的各种CCD延迟元件。 额外的级被保持在给定的电位以通过所有信号，从而不对增益有贡献，或连接到时钟信号，从而增加延迟。