公开(公告)号：US20070076292A1

公开(公告)日：2007-04-05

申请号：US11236169

申请日：2005-09-27

Applicant: Wei-Yu Su ,  Chuan-Chieh Lin

Inventor： Wei-Yu Su ,  Chuan-Chieh Lin

IPC: F21V9/04 ,  G02B5/08 ,  G02B5/20 ,  F21V9/06

CPC classification number: G03F7/70741 ,  G03F1/66

Abstract: A container includes a top wall, side walls, and a bottom wall, designed to enclose a space for storing an insulating object, the top, side and bottom walls having internal surfaces facing the enclosed space and external surface facing away from the enclosed space; and a metallic coating layer disposed on and substantially covering external surfaces of the top, side and bottom walls.

Abstract translation: 容器包括顶壁，侧壁和底壁，设计成封闭用于存储绝缘物体的空间，顶壁，侧壁和底壁具有面向封闭空间的内表面和背离封闭空间的外表面; 以及设置在顶壁，侧壁和底壁的外表面上并基本上覆盖顶壁，侧壁和底壁的外表面的金属涂层。

公开(公告)号：US20070072361A1

公开(公告)日：2007-03-29

申请号：US11421771

申请日：2006-06-02

Applicant: Chao-Chun Tu ,  Ming-Chieh Lin

Inventor： Chao-Chun Tu ,  Ming-Chieh Lin

IPC: H01L21/8242 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC classification number: H01L21/76816 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

Abstract translation: 一种用于减小半导体电容器中的漏电流的方法。 该方法包括提供用于收集电荷的顶板，提供用于收集与顶板相反的电荷的底板，提供用于在顶板和底板之间绝缘的介电层，提供顶部接触，提供底部接触， 提供多个通孔，包括用于将顶板连接到顶部触点的顶部通孔，以及用于将底板连接到底部触点的底部通孔; 以及分离通孔和相邻结构，使得它们的距离大于制造半导体电容器的半导体工艺的铸造设计规则的最小经过间隔要求。

公开(公告)号：US07175709B2

公开(公告)日：2007-02-13

申请号：US10847099

申请日：2004-05-17

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: C30B25/04

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20060286740A1

公开(公告)日：2006-12-21

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US20060170972A1

公开(公告)日：2006-08-03

申请号：US11229512

申请日：2005-09-20

Applicant: Chih-Chieh Lin

Inventor： Chih-Chieh Lin

IPC: H04N1/40

CPC classification number: H04N1/4053

Abstract: A system and method of processing an error diffusion half-tone image, which produces a halftone image in accordance with a continuous-tone image. The continuous tone image consists of a two-dimension array of pixels (i, j), where i, j indicate i-th row and j-th column of the image. The method includes: (A) selecting a threshold as a k-th color threshold in accordance with a value of a k-th color of a pixel (i, j); (B) comparing the value of the k-th color of the pixel (i, j) and the k-th color threshold; (C) outputting a bi-level value associated with the k-th color of the pixel (i, j) in accordance with a comparison result produced in step (B); (D) determining an error between the k-th color value of the pixel (i, j) and the bi-level value; (E) diffusing the error to k-th colors of pixels adjacent to the pixel (i, j).

Abstract translation: 一种处理误差扩散半色调图像的系统和方法，其产生根据连续色调图像的半色调图像。 连续色调图像由像素（i，j）的二维阵列组成，其中i，j表示图像的第i行和第j列。 该方法包括：（A）根据像素（i，j）的第k个颜色的值选择阈值作为第k个颜色阈值; （B）比较像素（i，j）的第k个颜色和第k个颜色阈值的值; （C）根据步骤（B）中产生的比较结果输出与像素（i，j）的第k个颜色相关联的双电平值; （D）确定像素（i，j）的第k个颜色值与双电平值之间的误差; （E）将误差扩散到与像素（i，j）相邻的像素的第k个颜色。

公开(公告)号：US20060052846A1

公开(公告)日：2006-03-09

申请号：US10935216

申请日：2004-09-08

Applicant: Chieh-Lin Liu ,  Hao-Hua Hung

Inventor： Chieh-Lin Liu ,  Hao-Hua Hung

IPC: A61N1/18

CPC classification number: A61N1/32

Abstract: A physical electrotherapy device comprised of a pulse switch selector; a first section pure pulse wave generating circuit; an intermittent pulse wave generating circuit; a third section high/low frequency alternating wave generating circuit; a rectifier, wave filter, and voltage stabilizer circuit; an LED output indication circuit; and a voltage regulating and efficiency enhancing output circuit. As such, the resulting electrotherapy device is non-injurious and capable of human body strengthening and health care maintenance.

Abstract translation: 一种物理电疗装置，包括脉冲开关选择器; 第一部分纯脉搏波发生电路; 间歇脉波产生电路; 第三部分高频/低频交流发生电路; 整流器，滤波器和稳压器电路; LED输出指示电路; 和电压调节和效率提高输出电路。 因此，所得到的电疗装置是无害的并且能够进行人体强化和保健维护。

公开(公告)号：US20060038606A1

公开(公告)日：2006-02-23

申请号：US10711916

申请日：2004-10-13

Applicant: Yin-Chang Chen ,  Yang-Chieh Lin

Inventor： Yin-Chang Chen ,  Yang-Chieh Lin

IPC: G05F1/10

CPC classification number: H02M3/073

Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.

Abstract translation: 能够将参考电压升压成输出电压的升压电路。 升压电路包括电连接到输出电压的主晶体管，电连接到输出电压的辅助晶体管，电连接到主晶体管的预充电电路和用于对主晶体管和辅助晶体管进行预充电的辅助晶体管 以及电连接到辅助晶体管的电压检测器和用于根据参考电压控制辅助晶体管的参考电压。

公开(公告)号：US06963114B2

公开(公告)日：2005-11-08

申请号：US10749273

申请日：2003-12-29

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: H01L29/41 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract translation: 包括位于衬底上的绝缘体，半导体特征和接触层的微电子器件。 半导体特征具有超过绝缘体的厚度，与绝缘体相对的第一表面和横跨至少一部分厚度的侧壁。 接触层具有在第一表面的至少一部分上延伸的第一构件和跨越侧壁的至少一部分的第二构件。

公开(公告)号：US06947300B2

公开(公告)日：2005-09-20

申请号：US10278379

申请日：2002-10-23

Applicant: Fu-Sheng Pai ,  Hung-Chieh Lin ,  Yuan-Fuan Lai

Inventor： Fu-Sheng Pai ,  Hung-Chieh Lin ,  Yuan-Fuan Lai

IPC: H02M7/48 ,  H02M7/493 ,  H02M7/00

CPC classification number: H02M7/493

Abstract: A parallel DC-to-AC power inverter system is provided. The parallel DC-to-AC power inverter system has a first DC-to-AC power inverter electrically connected in parallel with a second DC-to-AC power inverter, and each of the DC-to-AC power inverters includes an input port, an output port, a switching circuit electrically connected between the input port and the output port responsive to inverter control signals to convert a DC voltage at the input port to a first AC output voltage, an inductor-capacitor filter electrically connected to the switching circuit for filtering the first AC output voltage to an AC output voltage at output port, and a controller module for detecting an inductor current at the inductor-capacitor filter to generate an AC inductor current signal, for detecting the AC output voltage at the output terminals and transforming the AC output voltage to generate a first AC reference current signal, for detecting a load current at output port to generate an AC load current signal, for generating a second AC reference current signal by adding the first AC reference current signal to the AC load current signal, for performing a numerical operation of the second AC reference current signal of the first DC-to-AC power inverter and the second AC reference current signal of the second DC-to-AC power inverter to generate an AC reference current signal, and for generating the inverter control signals responsive to the AC reference current signal and the AC inductor current signal by sensing the inductor current at the inductor-capacitor filter. The related methods are also discussed.

Abstract translation: 提供并联的DC-AC电力逆变器系统。 并联DC-AC电力逆变器系统具有与第二DC-AC电力逆变器并联电连接的第一DC-AC电力逆变器，并且每个DC-AC电力逆变器包括输入端口 输出端口，电连接在输入端口和输出端口之间的开关电路，响应于逆变器控制信号，将输入端口处的DC电压转换为第一AC输出电压;电连接到开关电路的电感器 - 电容滤波器 用于将第一AC输出电压过滤到输出端口处的AC输出电压;以及控制器模块，用于检测电感器 - 电容滤波器处的电感器电流以产生AC电感器电流信号，用于检测输出端子处的AC输出电压，以及 变换交流输出电压以产生第一交流参考电流信号，用于检测输出端口处的负载电流以产生交流负载电流信号，用于产生第二交流参考电流 通过将第一AC参考电流信号加到AC负载电流信号上，用于执行第一DC-AC电力逆变器的第二AC参考电流信号和第二DC-AC电力信号的第二AC参考电流信号的数值运算， 以产生AC参考电流信号，并且通过感测电感器 - 电容滤波器处的电感器电流来响应于AC参考电流信号和AC电感器电流信号来产生逆变器控制信号。 还讨论了相关方法。

公开(公告)号：US20050158923A1

公开(公告)日：2005-07-21

申请号：US11081104

申请日：2005-03-15

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/68 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/78618 ,  H01L29/78654

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract translation: 一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210） （240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。 还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。