公开(公告)号：US20120122293A1

公开(公告)日：2012-05-17

申请号：US13359032

申请日：2012-01-26

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L21/02

CPC classification number: H01L27/0629 ,  H01L28/60

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract translation: 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。

公开(公告)号：US07919830B2

公开(公告)日：2011-04-05

申请号：US12062262

申请日：2008-04-03

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Kimball M. Watson

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Kimball M. Watson

IPC: H01L21/8222

CPC classification number: H01L29/41708 ,  H01L27/0629 ,  H01L27/0658 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/78

Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.

Abstract translation: 一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。 可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。 该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。

公开(公告)号：US07768055B2

公开(公告)日：2010-08-03

申请号：US11164634

申请日：2005-11-30

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Oliver Plouchart ,  Anthony K. Stamper

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Oliver Plouchart ,  Anthony K. Stamper

IPC: H01L29/94

CPC classification number: H01L23/5228 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

Abstract translation: 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

公开(公告)号：US20100149723A1

公开(公告)日：2010-06-17

申请号：US12706834

申请日：2010-02-17

Applicant: EBENEZER E. ESHUN ,  RONALD J. BOLAM ,  DOUGLAS D. COOLBAUGH ,  KEITH E. DOWNES ,  NATALIE B. FEILCHENFELD ,  ZHONG-XIANG HE

Inventor： EBENEZER E. ESHUN ,  RONALD J. BOLAM ,  DOUGLAS D. COOLBAUGH ,  KEITH E. DOWNES ,  NATALIE B. FEILCHENFELD ,  ZHONG-XIANG HE

IPC: H01G4/10 ,  H01G4/06 ,  H01G4/008

CPC classification number: H01L28/60

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract translation: 本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。 本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

公开(公告)号：US07728372B2

公开(公告)日：2010-06-01

申请号：US11382544

申请日：2006-05-10

Applicant: Ebenezer E. Eshun ,  Ronald J. Bolam ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Natalie B. Feilchenfeld ,  Zhong-Xiang He

Inventor： Ebenezer E. Eshun ,  Ronald J. Bolam ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Natalie B. Feilchenfeld ,  Zhong-Xiang He

IPC: H01L29/92

CPC classification number: H01L28/60

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract translation: 本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。 本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

公开(公告)号：US07700453B2

公开(公告)日：2010-04-20

申请号：US11697886

申请日：2007-04-09

Applicant: Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L21/20 ,  H01L21/8234 ,  H01L21/425

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: Method of fabricating a varactor that includes providing a semiconductor substrate, doping a lower region of the semiconductor substrate with a first dopant at a first energy level, doping a middle region of the semiconductor substrate with a second dopant at a second energy level lower than the first energy level, and doping an upper region of the semiconductor substrate with a third dopant at a third energy level lower than the second energy level.

Abstract translation: 一种制造变容二极管的方法，包括提供半导体衬底，以第一能级掺杂第一掺杂剂的半导体衬底的下部区域，在第二能级下掺杂第二掺杂剂的第二掺杂剂的中间区域; 第一能级，并且以比第二能级低的第三能级用第三掺杂剂掺杂半导体衬底的上部区域。

公开(公告)号：US07670921B2

公开(公告)日：2010-03-02

申请号：US11616955

申请日：2006-12-28

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

IPC: H01L21/4763

CPC classification number: H01G4/33 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/417 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

Abstract translation: 形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图和保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

公开(公告)号：US20100009509A1

公开(公告)日：2010-01-14

申请号：US12564482

申请日：2009-09-22

Applicant: Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L21/02

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

公开(公告)号：US07602068B2

公开(公告)日：2009-10-13

申请号：US11275604

申请日：2006-01-19

Applicant: Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L23/52

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

公开(公告)号：US20090065898A1

公开(公告)日：2009-03-12

申请号：US12271942

申请日：2008-11-17

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L29/00

CPC classification number: H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract translation: 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。