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    Silicon-on-insulator chip having an isolation barrier for reliability
    2.
    再颁专利
    Silicon-on-insulator chip having an isolation barrier for reliability 有权
    绝缘体上硅芯片具有可靠性的隔离屏障

    公开(公告)号：USRE40339E1

    公开(公告)日：2008-05-27

    申请号：US11004791

    申请日：2004-12-03

    申请人： Ronald J. Bolam ,  Subhash B. Kulkami ,  Dominic J. Schepis

    发明人： Ronald J. Bolam ,  Subhash B. Kulkami ,  Dominic J. Schepis

    IPC分类号： H01L29/01

    摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

    摘要翻译： 具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。 栅极沉积在硅层上方。 第一金属触点沉积在栅极上方以形成与栅极的电接触。 沉积第二和第三金属触点以形成与硅层的电接触。 隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。 隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。 还公开了制造SOI芯片的方法。

    Semiconductor On-Chip Repair Scheme for Negative Bias Temperature Instability
    4.
    发明申请
    Semiconductor On-Chip Repair Scheme for Negative Bias Temperature Instability 有权
    用于负偏压温度不稳定性的半导体片上修复方案

    公开(公告)号：US20090179689A1

    公开(公告)日：2009-07-16

    申请号：US11971937

    申请日：2008-01-10

    申请人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    发明人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    IPC分类号： H03K3/42 ,  H01L21/00

    CPC分类号： H01L23/345 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

    摘要翻译： 公开了半导体芯片结构的实施例和一种对于由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件而并入局部的片上修复方案的方法。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

    Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability
    5.
    发明授权
    Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
    电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性

    公开(公告)号：US06891359B2

    公开(公告)日：2005-05-10

    申请号：US10248506

    申请日：2003-01-24

    申请人： Kerry Bernstein ,  Ronald J. Bolam ,  Edward J. Nowak ,  Alvin W. Strong ,  Jody J. Van Horn ,  Ernest Y. Wu

    发明人： Kerry Bernstein ,  Ronald J. Bolam ,  Edward J. Nowak ,  Alvin W. Strong ,  Jody J. Van Horn ,  Ernest Y. Wu

    IPC分类号： G01N27/00 ,  G01R27/00 ,  G01R31/02 ,  G01R31/28

    CPC分类号： G01R31/2855

    摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.

    摘要翻译： 一种用于预测门可靠性的方法和系统。 该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。 优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。 更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分故障，确定第一个失败和第二个失败之间的关系，并且n th 失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。 如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。 这种关系可以量化。

    SOI pass gate leakage monitor
    6.
    发明授权
    SOI pass gate leakage monitor 失效
    SOI通孔泄漏监测器

    公开(公告)号：US06437594B1

    公开(公告)日：2002-08-20

    申请号：US09528350

    申请日：2000-03-17

    申请人： Ronald J. Bolam ,  Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

    发明人： Ronald J. Bolam ,  Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

    IPC分类号： G01R2722

    CPC分类号： G01R31/3004

    摘要： A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.

    摘要翻译： 这里描述了一种用于检测绝缘体上硅器件中的漏极泄漏的监视器及其使用方法。 脉冲发生器将信号提供给并联连接的一组缓冲器，该缓冲器将信号传递到一系列NFET的源极侧。 通过增加通道宽度来排列多个NFET。 NFET具有接地栅极，因此由于场效应而不会通过电流。 每个NFET连接到一个锁存器，并且锁存器最初设置为相同的状态。 当提供给NFET的信号从高到低时，通过每个NFET的通道将发生栅极泄漏。 如果通过任何给定NFET的漏极泄漏就足够了，锁存器将改变状态。 锁存器输出信号发送到移位寄存器，可以输出信息。 通过将显示器结合在芯片上，可以在制造过程中在线建立传递门泄漏公差和规格。

    Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
    7.
    发明授权
    Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture 失效
    绝缘体上硅芯片具有可靠性和制造工艺的隔离屏障

    公开(公告)号：US6133610A

    公开(公告)日：2000-10-17

    申请号：US9445

    申请日：1998-01-20

    申请人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

    CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648 ,  H01L21/76283

    摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

    摘要翻译： 具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。 栅极沉积在硅层上方。 第一金属触点沉积在栅极上方以形成与栅极的电接触。 沉积第二和第三金属触点以形成与硅层的电接触。 隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。 隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。 还公开了制造SOI芯片的方法。

    STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY
    8.
    发明申请
    STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY 有权
    半导体芯片修复方案结构的负偏差温度不稳定性

    公开(公告)号：US20090183131A1

    公开(公告)日：2009-07-16

    申请号：US12050990

    申请日：2008-03-19

    申请人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    发明人： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

    IPC分类号： G06F17/50

    CPC分类号： H01L23/345 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

    摘要翻译： 公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

    Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability
    10.
    发明授权
    Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability 有权
    制造具有隔离屏障的绝缘体上硅芯片的可靠性的工艺

    公开(公告)号：US06281095B1

    公开(公告)日：2001-08-28

    申请号：US09148918

    申请日：1998-09-04

    申请人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

    IPC分类号： H01L21301

    CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648

    摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

    摘要翻译： 具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。 栅极沉积在硅层上方。 第一金属触点沉积在栅极上方以形成与栅极的电接触。 沉积第二和第三金属触点以形成与硅层的电接触。 隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。 隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。 还公开了制造SOI芯片的方法。