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    METHOD OF FABRICATING DAMASCENE STRUCTURES
    6.
    发明申请
    METHOD OF FABRICATING DAMASCENE STRUCTURES 有权
    制备大分子结构的方法

    公开(公告)号：US20120115303A1

    公开(公告)日：2012-05-10

    申请号：US13354371

    申请日：2012-01-20

    申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

    发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

    IPC分类号： H01L21/4763 ,  H01L21/02

    CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

    摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

    摘要翻译： 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。

    Metal wiring structure for integration with through substrate vias
    7.
    发明授权
    Metal wiring structure for integration with through substrate vias 有权
    金属布线结构，用于与基板通孔集成

    公开(公告)号：US07968975B2

    公开(公告)日：2011-06-28

    申请号：US12188234

    申请日：2008-08-08

    申请人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

    发明人： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

    IPC分类号： H01L29/40 ,  H01L21/44

    CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

    摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。

    IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION
    8.
    发明申请
    IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION 有权
    通过WAVER VIAS DISHING CORRECTION进行IC芯片和设计结构

    公开(公告)号：US20100025857A1

    公开(公告)日：2010-02-04

    申请号：US12181467

    申请日：2008-07-29

    申请人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    发明人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC分类号： H01L23/48 ,  G06F9/45

    CPC分类号： H01L21/76898 ,  H01L21/76838 ,  H01L21/7684

    摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

    摘要翻译： 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

    Structure and design structure for high-Q value inductor and method of manufacturing the same
    9.
    发明授权
    Structure and design structure for high-Q value inductor and method of manufacturing the same 有权
    高Q值电感器的结构和设计结构及其制造方法

    公开(公告)号：US08232173B2

    公开(公告)日：2012-07-31

    申请号：US12917029

    申请日：2010-11-01

    申请人： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

    IPC分类号： H01L21/20

    CPC分类号： H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

    摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能性表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

    Method of fabricating damascene structures
    10.
    发明授权
    Method of fabricating damascene structures 有权

    公开(公告)号：US08119522B1

    公开(公告)日：2012-02-21

    申请号：US12941184

    申请日：2010-11-08

    申请人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

    发明人： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

    摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.