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    Process for single and multiple level metal-insulator-metal integration with a single mask
    4.
    发明授权
    Process for single and multiple level metal-insulator-metal integration with a single mask 有权
    单层和多层金属绝缘体金属与单一掩模集成的工艺

    公开(公告)号：US08435864B2

    公开(公告)日：2013-05-07

    申请号：US13432440

    申请日：2012-03-28

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L21/28

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 提供一种制造MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    Process for single and multiple level metal-insulator-metal integration with a single mask
    8.
    发明授权
    Process for single and multiple level metal-insulator-metal integration with a single mask 有权
    单层和多层金属绝缘体金属与单一掩模集成的工艺

    公开(公告)号：US08207568B2

    公开(公告)日：2012-06-26

    申请号：US11162661

    申请日：2005-09-19

    申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L29/92

    CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

    摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

    摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

    INTERDIGITATED VERTICAL PARALLEL CAPACITOR
    9.
    发明申请
    INTERDIGITATED VERTICAL PARALLEL CAPACITOR 有权
    INTERDIGITATED垂直并联电容器

    公开(公告)号：US20110049674A1

    公开(公告)日：2011-03-03

    申请号：US12548484

    申请日：2009-08-27

    申请人： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

    发明人： Roger A. Booth, Jr. ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/90 ,  H01L23/5223 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

    摘要翻译： 叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线 第一金属线并且与所述至少一个第二金属线分离。 所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。 多层交错结构可以垂直堆叠。 替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。 交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。