公开(公告)号：US20220139810A1

公开(公告)日：2022-05-05

申请号：US17117449

申请日：2020-12-10

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/778

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

公开(公告)号：US20220139809A1

公开(公告)日：2022-05-05

申请号：US17085137

申请日：2020-10-30

Applicant: GaN Systems Inc.

Inventor： Hossein MOUSAVIAN ,  Edward MACROBBIE

IPC: H01L23/482 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/861

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US20220115319A1

公开(公告)日：2022-04-14

申请号：US17065886

申请日：2020-10-08

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating overheating and potential damage to the semiconductor device. The masking layer is resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

公开(公告)号：US11183440B2

公开(公告)日：2021-11-23

申请号：US16705696

申请日：2019-12-06

Applicant: GaN Systems Inc.

Inventor： Juncheng Lu ,  Di Chen ,  Larry Spaziani ,  Peter Anthony Di Maso

IPC: H01L23/367 ,  H01L23/538 ,  H01L29/778 ,  H01L29/20 ,  H01L25/11 ,  H01L23/498

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

公开(公告)号：US11139373B2

公开(公告)日：2021-10-05

申请号：US16688008

申请日：2019-11-19

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40 ,  H01L29/778

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

公开(公告)号：US20210184567A1

公开(公告)日：2021-06-17

申请号：US17070309

申请日：2020-10-14

Applicant: GaN Systems Inc.

Inventor： Yajie QIU ,  Xuechao LIU

IPC: H02M3/07 ,  H02M7/06

Abstract: A circuit for a multi-voltage input AC/DC charger, such as a Universal AC input AC/DC charger, is provided, comprising a plurality of capacitors having different voltage ratings that are connected in parallel, and a switching circuit comprising input voltage sensing and comparator drive circuitry, to allow for selective connection of one or more of the plurality of capacitors, responsive to a sensed input voltage. Since bulk capacitors occupy a significant proportion of the volume of an AC/DC charger, this solution provides for a reduction in system volume, with associated improvement in the power density of an isolated AC/DC charger.

公开(公告)号：US20210184500A1

公开(公告)日：2021-06-17

申请号：US17094061

申请日：2020-11-10

Applicant: GaN Systems Inc.

Inventor： Tiefeng SHI ,  Paul WIENER

IPC: H02J50/12 ,  H01F38/14

Abstract: High efficiency resonator coils for large gap resonant wireless power transfer (WPT), and a coil design methodology are disclosed. Resonator coils comprise a coil topology defined by coil parameters in which turn dimensions, such as trace widths and spacings of each turn, are configured to reduce or minimize a variance of the z component of magnetic field, over an area of a charging plane at a specified distance, or distance range, from the coil. A Tx resonator coil comprises a capacitor arrangement of tuning and network-matching capacitors for improved coil-to-coil efficiency and end-to-end WPT system performance, e.g. for applications such as through-wall WPT, in the range of tens of watts to at least hundreds of watts. Planar resonator coil topologies are compatible with fabrication using low cost PCB technology, e.g. with multi-layer metal, to reduce losses and improve thermal performance.

公开(公告)号：US10985259B2

公开(公告)日：2021-04-20

申请号：US16212755

申请日：2018-12-07

Applicant: GaN Systems Inc.

Inventor： Thomas Macelwee

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/308

Abstract: GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

公开(公告)号：US20200328158A1

公开(公告)日：2020-10-15

申请号：US16380318

申请日：2019-04-10

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE

IPC: H01L23/532 ,  H01L29/20 ,  H01L29/778

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow and EaHigh that provide a conduction value below a required reliability threshold, e.g. ≤5×10−13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT for operation at >100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ≥75 C, EaLow is ≤0.2 eV and EaHigh is ≤1 eV, for improved reliability for high voltage, high temperature operation.

公开(公告)号：US20190081623A1

公开(公告)日：2019-03-14

申请号：US15704458

申请日：2017-09-14

Applicant: GaN Systems Inc.

Inventor： Ahmad MIZAN ,  Greg P. KLOWAK ,  Xiaodong CUI

IPC: H03K17/081 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522

Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.