公开(公告)号：US20060259666A1

公开(公告)日：2006-11-16

申请号：US11267669

申请日：2005-11-04

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G06F13/38

CPC classification number: G06F13/1684

Abstract: A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. The system further includes respective dedicated serial data and/or control busses configured to couple respective ones of the memory device sets to a memory controller external to the at least one memory module. The dedicated serial data and/or control busses may be configured to provide unbuffered access to the individual memory devices from the memory controller.

Abstract translation: 存储器系统包括在至少一个存储器模块上以组合排列的多个存储器件，每个存储器器件包括至少一个存储器件。 该系统还包括各自的专用串行数据和/或控制总线，其被配置为将存储器设备组中的相应存储器设备组耦合到至少一个存储器模块外部的存储器控​​制器。 专用串行数据和/或控制总线可以被配置为从存储器控制器提供对各个存储器设备的无缓冲的访问。

公开(公告)号：US07099175B2

公开(公告)日：2006-08-29

申请号：US10797667

申请日：2004-03-10

Applicant: Jae-Hyung Lee ,  Jung-Bae Lee

Inventor： Jae-Hyung Lee ,  Jung-Bae Lee

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/03

CPC classification number: G11C5/025 ,  G11C7/1045 ,  G11C2207/105

Abstract: In a semiconductor memory integrated circuit (IC), a plurality of first data IO pads, a plurality of address and instruction pads, and a plurality of second data IO/address pads, are arranged in groups adjacent each other. Each of the plurality of the second data IO/address pads is used as a second data IO pad in response to a control signal when packaged into a first package form and is used as an address pad in response to the control signal when packaged into a second package form. The semiconductor memory IC of the present invention can selectively use a portion of pads as data IO pads or address/instruction pads, and thus the IC is compatible for use with different types of packages. The semiconductor memory IC of the present invention further allows for simplified wire bonding when it is packaged into different types of packages, and thus the possibility of failure of the semiconductor memory device is reduced.

Abstract translation: 在半导体存储器集成电路（IC）中，多个第一数据IO焊盘，多个地址和指令焊盘以及多个第二数据IO /地址焊盘彼此相邻地排列。 多个第二数据IO /地址焊盘中的每一个作为响应于封装成第一封装形式的控制信号而被用作第二数据IO焊盘，并且当被封装成为第一数据IO /地址焊盘时被用作响应于控制信号的地址焊盘 第二包装形式。 本发明的半导体存储器IC可以选择性地使用焊盘的一部分作为数据IO焊盘或地址/指令焊盘，因此IC兼容于不同类型的封装。 本发明的半导体存储器IC在将其封装成不同类型的封装时进一步允许简化的引线接合，因此半导体存储器件的故障可能性降低。

公开(公告)号：US07085336B2

公开(公告)日：2006-08-01

申请号：US09875364

申请日：2001-06-05

Applicant: Jung-bae Lee ,  Kyu-hyoun Kim

Inventor： Jung-bae Lee ,  Kyu-hyoun Kim

IPC: H04L7/00

CPC classification number: H04L1/22 ,  H04L25/14

Abstract: A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the of the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.

Abstract translation: 信号传输电路和均衡两条信号传输线的差分延迟特性的方法。 可控延迟单元串联连接到第二线，以便通过增加其内部延迟来补偿。 辅助信号传输线在处理第一传输线的输入信号时复制第二传输线。 控制单元将第一传输线的输出信号与辅助信号传输线的输出信号进行比较，并动态地调整可控延迟单元的内部延迟，以获得连续同步。 数据锁存电路通过在每个数据路径中具有一个可控延迟单元来同步数据路径的延迟。

公开(公告)号：US07079444B2

公开(公告)日：2006-07-18

申请号：US10974951

申请日：2004-10-28

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C8/00

CPC classification number: G11C7/10 ,  G06F11/1044 ,  G06F13/1668 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/06

Abstract: A memory system using a simultaneous bi-directional input/output (SBD I/O) circuit on an address bus line. The memory system includes a first address I/O circuit and a second address I/O circuit, which are connected by the address bus line. The first address I/O circuit may be included in a controller, transmits an address signal to the address bus line, and receives an acknowledgement signal from the address bus line. The second address I/O circuit may be included in a memory device (such as dynamic random access memory (DRAM)), transmits the acknowledgement signal to the address bus line, and receives the address signal from the address bus line. The memory system may also include an error correction circuit unit which generates the acknowledgement signal indicating if an error is present in the address signal received by the second address I/O circuit.

Abstract translation: 在地址总线上使用同时双向输入/输出（SBD I / O）电路的存储器系统。 存储器系统包括通过地址总线连接的第一地址I / O电路和第二地址I / O电路。 第一地址I / O电路可以包括在控制器中，将地址信号发送到地址总线，并从地址总线接收确认信号。 第二地址I / O电路可以包括在存储器件（例如动态随机存取存储器（DRAM））中，将确认信号发送到地址总线，并从地址总线接收地址信号。 存储器系统还可以包括纠错电路单元，其产生指示在由第二地址I / O电路接收的地址信号中是否存在错误的确认信号。

公开(公告)号：US07054202B2

公开(公告)日：2006-05-30

申请号：US10792425

申请日：2004-03-03

Applicant: Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

Inventor： Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

IPC: G11C16/04

CPC classification number: G11C7/1078 ,  G11C7/1027 ,  G11C2207/107

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract translation: 集成电路存储器件包括被配置为并行地写入N个数据位的存储器单元阵列和被配置为从外部端子串行地接收2N个数据位的写入数据路径。 写数据路径包括2N个写入数据缓冲器，其被配置为存储2N个数据位，2N个开关和N个数据线，其被配置为将2N个开关中的至少N个连接到存储单元阵列以在其中写入N个数据位 平行。 可以提供减少数量的本地数据线和/或全局数据线。

公开(公告)号：US20050253615A1

公开(公告)日：2005-11-17

申请号：US10987706

申请日：2004-11-12

Applicant: Jung Sunwoo ,  Jung-Bae Lee

Inventor： Jung Sunwoo ,  Jung-Bae Lee

IPC: G11C29/00 ,  G01R31/02 ,  G01R31/317

CPC classification number: G01R31/31713 ,  G01R31/31723

Abstract: A semiconductor device includes an ODT (on die termination) pin coupled to a tester that applies a tester termination control signal thereon. The semiconductor device also includes a measure path that transmits the tester termination control signal from the ODT pin to an ODT circuit during measurement of a parameter of the semiconductor device. The ODT pin and the measure path advantageously allow for control of the ODT circuit by the tester for more accurate parameter characterization.

Abstract translation: 半导体器件包括耦合到测试器的ODT（管芯端子）引脚上的测试器端接控制信号。 半导体器件还包括测量路径，该测量路径在测量半导体器件的参数期间将测试器终止控制信号从ODT引脚传输到ODT电路。 ODT引脚和测量路径有利地允许由测试仪控制ODT电路以获得更准确的参数表征。

公开(公告)号：US20050226080A1

公开(公告)日：2005-10-13

申请号：US11082551

申请日：2005-03-17

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G11C7/10 ,  G11C5/00 ,  G11C7/00 ,  G11C29/38

CPC classification number: G11C5/04 ,  G11C29/028 ,  G11C29/38 ,  G11C29/50008 ,  G11C2207/2254

Abstract: Disclosed is a memory module and a method of calibrating an impedance of a semiconductor memory device of the memory module, where the memory module includes semiconductor memory devices each having a separate terminal for calibrating impedance characteristics, and a reference resistor commonly connected to the separate terminals, such that the number of reference resistors used in calibration of impedance characteristics of an off-chip driver or an on-die termination circuit of the semiconductor memory device is reduced.

Abstract translation: 公开了一种校准存储器模块的半导体存储器件的阻抗的存储器模块和方法，其中存储器模块包括各自具有用于校准阻抗特性的单独端子的半导体存储器件，以及通常连接到单独端子的参考电阻器 使得用于校准半导体存储器件的片外驱动器或片上终端电路的阻抗特性的参考电阻器的数量减少。

公开(公告)号：US20050122810A1

公开(公告)日：2005-06-09

申请号：US10991729

申请日：2004-11-18

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C7/12

Abstract: Methods for controlling the timing of a pre-charge operation in a memory device are provided. In embodiments of the present invention, the timing may be controlled by dynamically selecting a word line off time based on information about a number of column cycles. This may be accomplished, for example, by routing a word line disable signal via one of a first plurality of delay paths. The methods may further include dynamically selecting a bit line equalization start time based on the information about the number of column cycles. This may be accomplished, for example, by routing a bit line equalization start signal via one of a second plurality of delay paths. Pursuant to still further embodiments of the present invention, systems for controlling timing in a memory device are provided which include a control circuit that is configured to select a word line off time from a plurality of word line off times in response to a word line signal and information about a number of column cycles.

Abstract translation: 提供了用于控制存储器件中的预充电操作的定时的方法。 在本发明的实施例中，可以基于关于多个列周期的信息动态地选择字线关闭时间来控制定时。 这可以例如通过经由第一多个延迟路径中的一个来路由字线禁用信号来实现。 所述方法还可以包括基于关于列周期数的信息来动态地选择位线均衡开始时间。 这可以例如通过经由第二多个延迟路径之一路由位线均衡起始信号来实现。 根据本发明的另外的实施例，提供了一种用于控制存储器件中的定时的系统，其包括控制电路，其被配置为响应于字线信号从多个字线关闭时间选择字线关闭时间 以及关于多个列循环的信息。

公开(公告)号：US20050105294A1

公开(公告)日：2005-05-19

申请号：US10970016

申请日：2004-10-22

Applicant: Geun-hee Cho ,  Jung-bae Lee

Inventor： Geun-hee Cho ,  Jung-bae Lee

IPC: G11C11/40 ,  F21V1/00 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057

Abstract: A data output driver of a semiconductor memory device can minimize a difference in slew rate of an output signal according to a selected bit organization. The data output driver includes a pull-up driver and a pull-down driver. The pull-up driver pulls up an output terminal and the pull-down driver pulls down the output terminal. In particular, current driving capabilities of the pull-up driver and/or the pull-down driver are changed in response to bit organization information signals of the semiconductor memory device.

Abstract translation: 半导体存储器件的数据输出驱动器可以根据所选位组织来最小化输出信号的转换速率差。 数据输出驱动器包括一个上拉驱动器和一个下拉驱动器。 上拉驱动器拉出输出端子，下拉驱动器拉出输出端子。 特别地，上拉驱动器和/或下拉驱动器的当前驱动能力响应于半导体存储器件的位组织信息信号而改变。

公开(公告)号：US20050010841A1

公开(公告)日：2005-01-13

申请号：US10831702

申请日：2004-04-23

Applicant: Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

Inventor： Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

IPC: G11C7/10 ,  G11C29/14 ,  G11C29/48 ,  G11C29/00

CPC classification number: G11C29/14 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: The present invention provides a memory module, comprising: a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.

Abstract translation: 本发明提供了一种存储器模块，包括：用于写入和读取m位并行数据的多个半导体存储器件; 以及用于将n位串行数据转换成m位并行数据以输出到多个半导体存储器件的缓冲器，将m位并行数据转换成n位串行数据，以在第一外部部分输出 正常操作，缓冲2n位并行数据以输出到多个半导体存储器件，以及在测试操作期间缓冲m位并行数据以输出到第二外部部分。