公开(公告)号：US07485567B2

公开(公告)日：2009-02-03

申请号：US11670524

申请日：2007-02-02

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.

摘要翻译： 一种制造微电子电路的方法包括以下步骤：提供包括由第一布线层介电材料隔开的第一布线层导体的第一布线层; 在所述第一布线层上形成层状介电材料和牺牲材料的多个交替层; 以及在层介电材料和牺牲材料的交替层中形成多个互连开口和多个间隙开口。 互连开口形成在第一布线层导体上。 该方法还包括形成（i）包括第二布线层导体的金属导体，和（ii）互连开口处的互连; 并且通过间隙开口去除牺牲材料的层。

公开(公告)号：US07482270B2

公开(公告)日：2009-01-27

申请号：US11566848

申请日：2006-12-05

申请人： Wai-Kin Li ,  Haining Yang

发明人： Wai-Kin Li ,  Haining Yang

IPC分类号： H01L21/44

CPC分类号： H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

摘要： Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

摘要翻译： 通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。 然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。 退火步骤将多晶硅转化为硅化物。 由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。 使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

公开(公告)号：US20080303164A1

公开(公告)日：2008-12-11

申请号：US11758206

申请日：2007-06-05

申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在第二介电层中的空隙，停止在盖层上，其中，空隙以如下方式定位，以便隔离由于第一金属线的电迁移效应引起的结构损坏，包括一种或多种金属挤压的效果 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。

公开(公告)号：US20080135987A1

公开(公告)日：2008-06-12

申请号：US11609496

申请日：2006-12-12

申请人： Wai-Kin Li ,  Haining Yang

发明人： Wai-Kin Li ,  Haining Yang

IPC分类号： H01L21/38 ,  H01L23/58

CPC分类号： H01L21/76841 ,  H01L21/823842 ,  H01L21/823871 ,  H01L22/12 ,  H01L23/58 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

摘要翻译： 提供了具有在N型器件和P型器件之间的势垒区域的栅极导体结构，其中所述势垒区域最小化或消除了所述阻挡区域上的掺杂剂物质的交叉扩散。 阻挡区域包括栅极导体结构中的至少一个亚光刻间隙。 通过使用自组装共聚物在栅极导体结构上形成亚光刻图案掩模来形成亚光刻间隙。 根据一个实施例，至少一个亚光刻间隙是穿过栅极导体结构的宽度的狭缝或线。 亚光刻间隙足够深以使注入的掺杂剂从栅极导体的上部最小化或防止交叉扩散。 根据另一个实施例，亚光刻间隙具有足够的密度，使得在激活退火期间掺杂剂的交叉扩散减少或消除，使得Vt的变化最小化。

公开(公告)号：US07384852B2

公开(公告)日：2008-06-10

申请号：US11552641

申请日：2006-10-25

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8228

CPC分类号： H01L21/28123 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L29/66583 ,  H01L29/78

摘要： A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个晶体管的半导体结构，其中所述至少一个晶体管具有亚光刻沟道长度。 还提供了使用可以使用预制的硬掩模图案放置在特定位置的自组装嵌段共聚物来形成这种半导体结构的方法。

公开(公告)号：US20080048271A1

公开(公告)日：2008-02-28

申请号：US11467186

申请日：2006-08-25

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L29/76 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/7843

摘要： A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.

摘要翻译： 提供了一种代替CMOS器件中常规应力衬垫的低k应力衬垫。 在一个实施例中，提供压缩的低k应力衬垫，其可以改善pFET器件中的空穴迁移率。 这种压缩低k材料的紫外线暴露导致低k应力衬垫的极性从压缩变为拉伸。 使用这种拉伸的低k应力衬垫提高nFET器件中的电子迁移率。

公开(公告)号：US20070296027A1

公开(公告)日：2007-12-27

申请号：US11425516

申请日：2006-06-21

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/7843

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having a continuous dielectric stressor layer containing regions of opposite stresses. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A continuous dielectric stressor layer, which overlays both the at least one n-FET and the at least one p-FET, contains a first, tensilely stressed region that selectively overlays the at least one n-FET and a second, compressively stressed region that selectively overlays the at least one p-FET. Such a continuous dielectric stressor layer can be readily formed by first depositing a continuous, compressively stressed dielectric layer and then converting a selected region of such a layer from being compressively stressed to being tensilely stressed by ultraviolet (UV) exposure.

摘要翻译： 本发明涉及具有包含相反应力区域的连续介电应力层的互补金属氧化物半导体（CMOS）器件。 具体地，本发明的每个CMOS器件包括至少一个n沟道场效应晶体管（n-FET）和至少一个p沟道场效应晶体管（p-FET）。 覆盖至少一个n-FET和至少一个p-FET两者的连续介电应力层含有选择性地覆盖至少一个n-FET和第二压缩应力区的第一拉伸应力区， 选择性地覆盖所述至少一个p-FET。 这种连续的介电应力层可以容易地通过首先沉积连续的压缩应力介电层，然后将这种层的选定区域从压缩应力转变成被紫外（UV）曝光拉伸应力而容易地形成。

公开(公告)号：US20070293041A1

公开(公告)日：2007-12-20

申请号：US11424963

申请日：2006-06-19

申请人： Haining Yang ,  Wai-Kin Li

发明人： Haining Yang ,  Wai-Kin Li

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/31144 ,  G03F7/0002 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

摘要： A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w

摘要翻译： 提供了一种用于进行子光刻特征图案化的器件结构的方法。 首先，通过在器件结构的上表面上的光刻和蚀刻来形成包含直径d的一个或多个掩模开口的光刻图案掩模层。 接下来，将一层自组装嵌段共聚物施加在光刻图案化的掩模层上，然后退火以在每个掩模开口内形成直径为w的单个单元聚合物嵌段，条件是w

公开(公告)号：US20070037325A1

公开(公告)日：2007-02-15

申请号：US11581544

申请日：2006-10-16

申请人： Wai-Kin Li ,  Colin Brodsky ,  Steven Scheer

发明人： Wai-Kin Li ,  Colin Brodsky ,  Steven Scheer

IPC分类号： H01L21/84

CPC分类号： G03F7/11 ,  H01L21/312

摘要： A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposited film is then stabilized to form a stabilized film. Thereafter, the stabilized film is then thinned to a second thickness, such that the resulting film now has a smaller thickness than the thickness at which the initially deposited film would begin to dewet from the substrate. However, as a result of the prior stabilization, the reduced thickness film remains free of dewetting defects.

摘要翻译： 提供了一种形成薄膜的方法，其中具有第一厚度的膜沉积在基底上，其中第一厚度大于初始沉积的膜开始从基底露出的厚度。 然后将初始沉积的膜稳定以形成稳定的膜。 此后，将稳定的薄膜变薄至第二厚度，使得所得到的薄膜现在具有比初始沉积的薄膜将从基底开始露出的厚度更小的厚度。 然而，由于现有的稳定性，减薄膜仍然没有脱湿缺陷。

公开(公告)号：US07132316B2

公开(公告)日：2006-11-07

申请号：US11029812

申请日：2005-01-05

申请人： Wai-Kin Li ,  Colin J. Brodsky ,  Steven A. Scheer

发明人： Wai-Kin Li ,  Colin J. Brodsky ,  Steven A. Scheer

IPC分类号： H01L21/00 ,  H01L21/8238

CPC分类号： G03F7/11 ,  H01L21/312

摘要： A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposited film is then stabilized to form a stabilized film. Thereafter, the stabilized film is then thinned to a second thickness, such that the resulting film now has a smaller thickness than the thickness at which the initially deposited film would begin to dewet from the substrate. However, as a result of the prior stabilization, the reduced thickness film remains free of dewetting defects.