公开(公告)号：US20210319836A1

公开(公告)日：2021-10-14

申请号：US17224024

申请日：2021-04-06

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Enrico CASTALDO ,  Francesca GRANDE ,  Santi Nunzio Antonino PAGANO ,  Giuseppe NASTASI ,  Franco ITALIANO

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11529

Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

公开(公告)号：US11143701B2

公开(公告)日：2021-10-12

申请号：US16909696

申请日：2020-06-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US11120887B2

公开(公告)日：2021-09-14

申请号：US17096090

申请日：2020-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Eva ,  Jean-Michel Gril-Maffre

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/44

Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.

公开(公告)号：US20210248104A1

公开(公告)日：2021-08-12

申请号：US17143679

申请日：2021-01-07

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Manoj KUMAR ,  Kailash KUMAR ,  Nicolas DEMANGE

IPC: G06F13/42 ,  G06F1/06

Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

公开(公告)号：US11075246B2

公开(公告)日：2021-07-27

申请号：US15818496

申请日：2017-11-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara

IPC: H01L27/16 ,  H01L35/32

Abstract: Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically intercoupled by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically coupled in series and thermally coupled in parallel and contained within the said region subjected to the said temperature gradient.

公开(公告)号：US20210195404A1

公开(公告)日：2021-06-24

申请号：US17122782

申请日：2020-12-15

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Alexandre TRAMONI ,  Pierre RIZZO ,  Olivier VAN NIEUWENHUYZE

IPC: H04W8/22 ,  H04W4/029 ,  H04W4/80

Abstract: A method of configuration of a mobile terminal including a near-field communication device is provided. The method includes determining the geographic position of the mobile terminal. The method further includes selecting, from a configuration table stored in an internal memory of the mobile terminal, a set of one or a plurality of configuration parameters of the near-field communication device according to the geographic position, and applying a selected set of parameters to the near-field communication device.

公开(公告)号：US11031550B2

公开(公告)日：2021-06-08

申请号：US16457855

申请日：2019-06-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US20210150696A1

公开(公告)日：2021-05-20

申请号：US16687349

申请日：2019-11-18

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Laurent BIDAULT

IPC: G06T7/00 ,  G06K9/62 ,  G06N3/04 ,  G06N3/08

Abstract: A device includes image generation circuitry and convolutional-neural-network circuitry. The image generation circuitry, in operation, generates a digital image representation of a wafer defect map (WDM). The convolutional-neural-network circuitry, in operation, generates a defect classification associated with the WDM based on: the digital image representation of the WDM and a data-driven model associating WDM images with classes of a defined set of classes of wafer defects and generated using a training data set augmented based on defect pattern orientation types associated with training images.

公开(公告)号：US11004785B2

公开(公告)日：2021-05-11

申请号：US16546569

申请日：2019-08-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US10991710B2

公开(公告)日：2021-04-27

申请号：US16391768

申请日：2019-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  G11C5/06 ,  H01L27/11565

Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.