公开(公告)号：US06441349B1

公开(公告)日：2002-08-27

申请号：US09558643

申请日：2000-04-26

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Sanjay K. Yedur

IPC分类号： H05B368

CPC分类号： H01L21/67103

摘要： A system and method for facilitating uniform heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material. The system can include at least one heating element and a heat transfer fluid, the heating element heating the heat transfer fluid, which in turn heats the material. The transfer fluid more evenly distributes the heat from the heating element, which can have hot and cold spots at the material.

摘要翻译： 提供了一种用于促进材料的均匀加热温度的系统和方法。 该材料可以是光致抗蚀剂，顶部或底部抗反射涂层，低K电介质材料，SOG或其它旋涂材料。 该系统可以包括至少一个加热元件和传热流体，该加热元件加热该传热流体，该热传导流体依次加热该材料。 传输流体更均匀地分配来自加热元件的热​​量，其可以在材料上具有热点和冷点。

公开(公告)号：US06335152B1

公开(公告)日：2002-01-01

申请号：US09564408

申请日：2000-05-01

申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03F738

CPC分类号： G03F7/38

摘要： In one embodiment, the present invention relates to a method of processing an irradiated photoresist involving the steps of placing a substrate having the irradiated photoresist thereon at a first temperature in a rapid thermal anneal furnace; heating the substrate having the irradiated photoresist thereon to a second temperature within about 0.1 seconds to about 10 seconds; cooling the substrate having the irradiated photoresist thereon to a third temperature in a rapid thermal annealing furnace within about 0.1 seconds to about 10 seconds; and developing the irradiated photoresist, wherein the second temperature is higher than the first temperature and the third temperature. In another embodiment, the present invention relates to a system of processing a photoresist, containing a source of actinic radiation and a mask for selectively irradiating a photoresist; a rapid thermal annealing furnace for rapidly heating and rapidly cooling a selectively irradiated photoresist, wherein the rapid heating and rapid cooling are independently conducted within about 0.1 seconds to about 10 seconds; and a developer for developing a rapid thermal annealing furnace heated and selectively irradiated photoresist into a patterned photoresist.

摘要翻译： 在一个实施方案中，本发明涉及一种处理被照射的光致抗蚀剂的方法，包括以下步骤：在快速热退火炉中将具有照射光致抗蚀剂的基底在第一温度下放置; 将其上具有照射的光致抗蚀剂的基板加热至约0.1秒至约10秒的第二温度; 将快速热退火炉中具有照射光致抗蚀剂的基板冷却至约0.1秒至约10秒的第三温度; 并且显影所述被照射的光致抗蚀剂，其中所述第二温度高于所述第一温度和所述第三温度。 在另一个实施方案中，本发明涉及一种处理含有光化辐射源的光致抗蚀剂的系统和用于选择性地照射光致抗蚀剂的掩模; 快速热退火炉，用于快速加热和快速冷却选择性照射的光致抗蚀剂，其中快速加热和快速冷却在约0.1秒至约10秒内独立进行; 以及用于将快速热退火炉加热并选择性地照射光致抗蚀剂的显影剂加工成图案化的光致抗蚀剂。

公开(公告)号：US06322009B1

公开(公告)日：2001-11-27

申请号：US09429992

申请日：1999-10-29

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： B05B900

CPC分类号： H01L21/6708 ,  H01L21/67051

摘要： A combination nozzle for applying a developer material and a washing solution material at different time intervals to a photoresist material layer disposed on a wafer is provided. The combination nozzle includes a number of developer nozzle tips connected to a developer supply line and a number of washing solution nozzle tips connected to a washing solution supply line. The developer supply line and the washing solution supply line ensure that the developer material and the washing solution material are always substantially isolated from one another. Furthermore, the developer nozzle tips and the washing solution nozzle tips are arranged so that developer material and washing solution material do not come into contact with one another. The volume of the material and the volume flow of the material can be controlled by electronically controlled valves.

摘要翻译： 提供了用于将显影剂材料和洗涤液材料以不同的时间间隔施加到设置在晶片上的光致抗蚀剂材料层的组合喷嘴。 组合喷嘴包括连接到显影剂供应管线的多个显影剂喷嘴尖端和连接到洗涤溶液供应管线的多个洗涤溶液喷嘴尖端。 显影剂供应管线和洗涤溶液供应管线确保显影剂材料和洗涤液材料总是基本上彼此隔离。 此外，显影剂喷嘴尖端和洗涤溶液喷嘴尖端被布置成使得显影剂材料和洗涤液材料彼此不接触。 材料的体积和材料的体积流量可以通过电子控制阀来控制。

公开(公告)号：US06297143B1

公开(公告)日：2001-10-02

申请号：US09426743

申请日：1999-10-25

申请人： David K. Foote ,  Bharath Rangarajan ,  Fei Wang ,  Steven K. Park

发明人： David K. Foote ,  Bharath Rangarajan ,  Fei Wang ,  Steven K. Park

IPC分类号： H01L214763

CPC分类号： H01L27/11568 ,  H01L27/11517

摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.

摘要翻译： 用于制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的掩模层。 此后，进行蚀刻处理以在半导体衬底中形成沟槽。 接下来，去除掩模层，并且用氧化硅层填充半导体衬底中的沟槽。 为了形成位线氧化层，利用平面化工艺来平坦化氧化硅层并形成与半导体衬底的上表面连续的平面。

公开(公告)号：US06269322B1

公开(公告)日：2001-07-31

申请号：US09266361

申请日：1999-03-11

申请人： Michael K. Templeton ,  Bharath Rangarajan ,  Kathleen R. Early ,  Terry Manchester

发明人： Michael K. Templeton ,  Bharath Rangarajan ,  Kathleen R. Early ,  Terry Manchester

IPC分类号： G03B2742

CPC分类号： G03F9/70

摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design and first and second alignment marks. The second alignment mark is symmetric to the first alignment mark such that a reticle center point is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark in wafer alignment substantially facilitates mitigation of overlay error.

摘要翻译： 本发明涉及晶圆对准。 使用掩模版，其包括设计和第一和第二对准标记。 第二对准标记与第一对准标记对称，使得标线片中心点是第一和第二对准标记的中点。 将第一对准标记印刷在晶片的表面层上。 第二对准标记以与第一对准标记偏移的方式印刷在表面层上。 确定虚拟对准标记，虚拟对准标记是打印的第一和第二对准标记的中点。 采用虚拟对准标记以便于对准晶片。 第一和第二对准标记之间的对称关系导致相对于虚拟对准标记由于标线旋转和/或透镜放大而导致的标记的打印错误的否定。 在晶片对准中使用虚拟对准标记基本上有助于减轻重叠误差。

公开(公告)号：US06261904B1

公开(公告)日：2001-07-17

申请号：US09596449

申请日：2000-06-19

申请人： Tuan Pham ,  Bharath Rangarajan ,  Mike Templeton

发明人： Tuan Pham ,  Bharath Rangarajan ,  Mike Templeton

IPC分类号： H01L21336

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供了一种存储器件，其包括具有在浮置栅极之间具有隔离间隔物的双ONO浮置栅极的浮栅晶体管。 还提供了用于制造根据本发明的存储器件的工艺。

公开(公告)号：US06245493B1

公开(公告)日：2001-06-12

申请号：US09205738

申请日：1998-12-04

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur ,  Michael K. Templeton ,  Christopher F. Lyons

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur ,  Michael K. Templeton ,  Christopher F. Lyons

IPC分类号： G03F700

CPC分类号： H01L21/0276 ,  G03F7/091 ,  G03F7/16 ,  H01L21/3105

摘要： A method for creating a roughened surface on a material exposed to light during a photolithographic process is provided. The roughened surface is created on a surface of the material via a plasma etch process. The roughened surface diffuses light incident to the material such that the diffused light causes insubstantial damage to a photoresist subsequently formed on the material.

摘要翻译： 提供了一种在光刻过程中在暴露于光的材料上产生粗糙表面的方法。 通过等离子体蚀刻工艺在材料的表面上形成粗糙表面。 粗糙表面扩散入射到材料的光，使得漫射的光对随后在材料上形成的光致抗蚀剂造成非实质的损坏。

公开(公告)号：US06238830B1

公开(公告)日：2001-05-29

申请号：US09429994

申请日：1999-10-29

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh

IPC分类号： G03F900

CPC分类号： G03F7/70875 ,  G01Q30/10 ,  G01Q80/00 ,  H01J2237/31759 ,  Y10S977/855

摘要： A system for monitoring and regulating a photoresist temperature in a maskless lithography pattern transfer process is disclosed. The system includes a photoresist layer overlying a substrate and a material associated with the photoresist layer, wherein the material exhibits a transformation over variations in temperature. The system also includes a detection system for detecting the transformation in the material and a processor operatively coupled to the detection system. The processor receives information associated with the detected transformation and uses the information to control a tool being used for the pattern transfer, thereby reducing variations in temperature in the resist during pattern transfer. In addition, a method of monitoring and regulating a photoresist temperature in a maskless lithography pattern transfer process is disclosed. The method includes associating a material having a characteristic which varies over variations in temperature with a photoresist layer which overlies a substrate and detecting the characteristic during the pattern transfer process. Once detected a temperature of a portion of the photoresist layer is determined using the detected characteristic and an operation of a writing tool which performs the pattern transfer process in response to the photoresist layer temperature is controlled in response thereto.

摘要翻译： 公开了一种用于在无掩模光刻图案转印工艺中监测和调节光刻胶温度的系统。 该系统包括覆盖衬底的光致抗蚀剂层和与光致抗蚀剂层相关联的材料，其中材料表现出与温度变化的转变。 该系统还包括用于检测材料中的变换的检测系统和可操作地耦合到检测系统的处理器。 处理器接收与检测到的变换相关联的信息，并使用该信息来控制用于图案转印的工具，由此减少图案转印期间抗蚀剂的温度变化。 此外，公开了一种在无掩模光刻图案转印工艺中监测和调节光刻胶温度的方法。 该方法包括将具有随温度变化变化的特性的材料与覆盖在衬底上的光致抗蚀剂层相关联，并且在图案转移过程期间检测特性。 一旦检测到，使用检测到的特性确定光刻胶层的一部分的温度，并响应于光致抗蚀剂层温度来控制执行图案转印处理的写入工具的操作。

公开(公告)号：US06221777B1

公开(公告)日：2001-04-24

申请号：US09329154

申请日：1999-06-09

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Ursula Q. Quinto

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Ursula Q. Quinto

IPC分类号： H01L2100

CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L21/76816

摘要： A reverse lithographic process is provided for more densely packing semiconductors onto a semiconductor wafer. A semiconductor wafer having a dielectric covered semiconductor device has a photoresist deposited which is patterned with vias in closely packed rows and columns. The resist is developed and trimmed to form via photoresist structures. A non-photosensitive polymer is deposited over the via photoresist structures and, when hardened, is subject to planarizing to expose the via photoresist structures. The via photoresist structures are removed and leave a reverse image patterned polymer. The photoresist is removed leaving the reverse image patterned polymer, which is then used to etch the dielectric to form vias to the semiconductor device.

摘要翻译： 提供反向光刻工艺用于在半导体晶片上更密集地堆叠半导体。 具有电介质覆盖的半导体器件的半导体晶片具有沉积的光致抗蚀剂，其以紧密堆积的行和列形成通孔。 抗蚀剂被显影和修整以通过光致抗蚀剂结构形成。 非光敏聚合物沉积在通孔光致抗蚀剂结构上，并且当硬化时，进行平面化以暴露通孔光致抗蚀剂结构。 去除通孔光致抗蚀剂结构并留下反向图案图案化的聚合物。 除去光致抗蚀剂留下反向图案图案化的聚合物，然后将其用于蚀刻电介质以形成到半导体器件的通孔。

公开(公告)号：US06168993A

公开(公告)日：2001-01-02

申请号：US09487922

申请日：2000-01-19

申请人： David K. Foote ,  Bharath Rangarajan ,  George Kluth ,  Fei Wang

发明人： David K. Foote ,  Bharath Rangarajan ,  George Kluth ,  Fei Wang

IPC分类号： H01L218247

CPC分类号： H01L29/66825

摘要： A process for fabricating a semiconductor device includes the step of processing a patterned resist layer to vary the lateral dimensions of the patterned resist layer while forming doped regions in a semiconductor substrate. A graded junction profile is formed by creating a patterned resist layer having a first substantially vertical edge surface. A doping process is carried out to form a first doped region in the semiconductor substrate having a junction profile substantially continuous with the first substantially vertical edge surface. The patterned resist layer is processed to form a second substantially vertical edge surface, which is laterally displaced from the first substantially vertical edge surface. A doping process is carried out to form a second doped region having a junction profile that is substantially continuous with the second substantially vertical edge surface. The junction profiles of the first and second doped regions form a graded junction within the semiconductor substrate. The process can be repeated to form a wide variety of graded junction profiles within a semiconductor substrate.

摘要翻译： 制造半导体器件的方法包括处理图案化的抗蚀剂层以改变图案化的抗蚀剂层的横向尺寸同时在半导体衬底中形成掺杂区域的步骤。 通过产生具有第一基本上垂直的边缘表面的图案化抗蚀剂层来形成分级结型材。 执行掺杂工艺以在半导体衬底中形成具有与第一基本上垂直的边缘表面基本连续的接合轮廓的第一掺杂区域。 图案化的抗蚀剂层被加工成形成第二基本上垂直的边缘表面，其从第一基本上垂直的边缘表面横向移位。 进行掺杂工艺以形成具有与第二基本上垂直的边缘表面基本连续的接合轮廓的第二掺杂区域。 第一和第二掺杂区的结型材在半导体衬底内形成渐变结。 可以重复该过程以在半导体衬底内形成多种渐变连接轮廓。