公开(公告)号：US20080044112A1

公开(公告)日：2008-02-21

申请号：US11974766

申请日：2007-10-16

申请人： Brent Anderson

发明人： Brent Anderson

IPC分类号： B65D33/16 ,  B65D33/22

CPC分类号： B65D33/2541 ,  B31B70/8132 ,  B65D33/2591 ,  Y10T24/2534 ,  Y10T24/2596

摘要： The present invention provides a recloseable bag, the bag having a mouth and including a closure at the mouth, the closure having a first end and a second end. The recloseable bag also includes a first crushed section at the first end of the closure, the closure further including an intact portion. It also includes a first transition area between the first crushed section and the intact portion, and a sealing material in the first transition area.

摘要翻译： 本发明提供了一种可重新封闭的袋子，该袋子具有口部并且在口部包括封闭件，该封闭件具有第一端部和第二端部。 可再封闭袋还包括在封闭件的第一端处的第一破碎部分，封闭件还包括完整部分。 它还包括在第一破碎部分和完整部分之间的第一过渡区域和第一过渡区域中的密封材料。

公开(公告)号：US07305742B2

公开(公告)日：2007-12-11

申请号：US10293145

申请日：2002-11-13

申请人： Brent Anderson

发明人： Brent Anderson

IPC分类号： A44B19/16 ,  A44B19/36

CPC分类号： B65D33/2541 ,  B31B70/8132 ,  B65D33/2591 ,  Y10T24/2534 ,  Y10T24/2596

摘要： The present invention provides a recloseable bag, the bag having a mouth and including a closure at the mouth, the closure having a first end and a second end. The recloseable bag also includes a first crushed section at the first end of the closure, the closure further including an intact portion. It also includes a first transition area between the first crushed section and the intact portion, and a sealing material in the first transition area.

摘要翻译： 本发明提供了一种可重新封闭的袋子，该袋子具有口部并且在口部包括封闭件，该封闭件具有第一端部和第二端部。 可再封闭袋还包括在封闭件的第一端处的第一破碎部分，封闭件还包括完整部分。 它还包括在第一破碎部分和完整部分之间的第一过渡区域和第一过渡区域中的密封材料。

公开(公告)号：US20070269950A1

公开(公告)日：2007-11-22

申请号：US11830872

申请日：2007-07-31

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

摘要： A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second gate conductors on either sidewall of the fin are formed and include symmetric multiple layers of conductive material. An insulator is formed above the fin by either oxidizing conductive material deposited on the fin or by removing conductive material deposited on the fin and filling in the resulting space with an insulating material. An insulating layer is deposited over the gate conductors and the insulator. A first gate contact opening is etched in the insulating layer above the first gate. A second gate contact opening is etched in the BOX layer below the second gate.

摘要翻译： 双门控鳍型场效应晶体管（FinFET）结构具有电隔离栅极。 在制造FinFET结构的方法中，在衬底上的掩埋氧化物（BOX）层上形成在每个侧壁上具有与中心沟道区对应的栅极电介质的鳍。 形成翅片的任一侧壁上的独立的第一和第二栅极导体，并且包括对称的多层导电材料。 通过对沉积在散热片上的导电材料进行氧化或者去除沉积在散热片上的导电材料并用绝缘材料填充所得到的空间，在翅片之上形成绝缘体。 绝缘层沉积在栅极导体和绝缘体上。 在第一栅极上方的绝缘层中蚀刻第一栅极接触开口。 在第二栅极下方的BOX层中蚀刻第二栅极接触开口。

公开(公告)号：US20070264729A1

公开(公告)日：2007-11-15

申请号：US11382489

申请日：2006-05-10

申请人： Brent Anderson ,  Shahid Butt ,  Allen Gabor ,  Patrick Lindo ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Shahid Butt ,  Allen Gabor ,  Patrick Lindo ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/20

摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.

摘要翻译： 一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。 该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数 在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。

公开(公告)号：US20070231987A1

公开(公告)日：2007-10-04

申请号：US11761438

申请日：2007-06-12

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

摘要翻译： 翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。 该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。 通道扩展增加了鳍片的通道部分的电容。

公开(公告)号：US20070184602A1

公开(公告)日：2007-08-09

申请号：US11689549

申请日：2007-03-22

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/42384 ,  H01L29/785

摘要： Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs has a fin with a lower mobility top surface. To inhibit inversion of the top surface, this MOSFET has a gate dielectric layer with a thicker region on the top surface than it does on the opposing sidewall surfaces. Additionally, several techniques for forming the thicker region of the gate dielectric layer are also disclosed.

摘要翻译： 这里公开了在同一衬底上形成有两个不同类型的三栅极MOSFET的结构。 每个MOSFET包括对于特定类型的MOSFET具有最佳移动性的鳍。 由于用于在相同衬底上形成具有不同结晶取向的鳍片的工艺，所以MOSFET中的一个具有具有较低迁移率顶表面的翅片。 为了抑制顶表面的反转，该MOSFET具有栅极电介质层，在顶表面上具有比在相对侧壁表面上更厚的区域。 此外，还公开了用于形成栅极电介质层的较厚区域的几种技术。

公开(公告)号：US20070122957A1

公开(公告)日：2007-05-31

申请号：US11164651

申请日：2005-11-30

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

摘要翻译： 为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或 接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化 的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

公开(公告)号：US20070105326A1

公开(公告)日：2007-05-10

申请号：US11164070

申请日：2005-11-09

申请人： Brent Anderson ,  Andres Bryant ,  Myung-hee Na ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Myung-hee Na ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/78621 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772

摘要： An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.

摘要翻译： 用于制造旋转场效应晶体管的装置和方法。 该方法包括提供包括彼此不平行的第一栅极结构和第二栅极结构的衬底。 该方法还包括执行基本上与第一栅极结构的边缘正交的第一离子注入以形成第一杂质区域，并且在不同于第一离子注入的方向上执行第二离子注入并且基本上垂直于第 第二栅极结构，以在第二栅极结构的边缘下方形成第二杂质区域。

公开(公告)号：US07178754B2

公开(公告)日：2007-02-20

申请号：US10124940

申请日：2002-04-17

申请人： Brent Anderson

发明人： Brent Anderson

IPC分类号： B65H75/28

CPC分类号： B65H75/14 ,  A63H27/002 ,  B65H75/18

摘要： The present invention provides a balloon anchor including a spool having opposing sides, a pair of flanges, one flange extending from each opposing side of the spool, at least one of the flanges having a cutout section, the cutout section having a first side and a second side; and a hook extending from the second side of the cutout section.

摘要翻译： 本发明提供了一种球囊锚固件，其包括具有相对侧面的卷轴，一对凸缘，从卷轴的每个相对侧延伸的一个凸缘，至少一个凸缘具有切口部分，该切口部分具有第一面和 第二面 以及从所述切口部的第二侧延伸的钩。

公开(公告)号：US20070034971A1

公开(公告)日：2007-02-15

申请号：US11161623

申请日：2005-08-10

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/42384 ,  H01L29/785

摘要： Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs has a fin with a lower mobility top surface. To inhibit inversion of the top surface, this MOSFET has a gate dielectric layer with a thicker region on the top surface than it does on the opposing sidewall surfaces. Additionally, several techniques for forming the thicker region of the gate dielectric layer are also disclosed.

摘要翻译： 这里公开了在同一衬底上形成有两个不同类型的三栅极MOSFET的结构。 每个MOSFET包括对于特定类型的MOSFET具有最佳移动性的鳍。 由于用于在相同衬底上形成具有不同结晶取向的鳍片的工艺，所以MOSFET中的一个具有具有较低迁移率顶表面的翅片。 为了抑制顶表面的反转，该MOSFET具有栅极电介质层，在顶表面上具有比在相对侧壁表面上更厚的区域。 此外，还公开了用于形成栅极电介质层的较厚区域的几种技术。