公开(公告)号：US06462417B1

公开(公告)日：2002-10-08

申请号：US09772750

申请日：2001-01-29

申请人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Minh Van Ngo ,  Suzette K. Pangrle

发明人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Minh Van Ngo ,  Suzette K. Pangrle

IPC分类号： H01L2348

CPC分类号： H01L21/76844 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53209 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an alloy-barrier layer lining the channel opening, and a conductor core filling the channel opening. An alloy layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form an alloy-barrier to diffusion of the material of the conductor core to the channel dielectric layer. The alloy-barrier layer is reacted with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.

摘要翻译： 提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有通道开口，衬在沟道开口的合金阻挡层和填充沟道开口的导体芯。 沉积合金层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成对导体芯的材料扩散到沟道介电层的合金阻挡层。 合金阻挡层与导体芯和沟道电介质层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯在双重嵌入式集成电路中的芯体扩散。

公开(公告)号：US06451647B1

公开(公告)日：2002-09-17

申请号：US10100819

申请日：2002-03-18

申请人： Chih-Yuh Yang ,  Minh Van Ngo

发明人： Chih-Yuh Yang ,  Minh Van Ngo

IPC分类号： H01L218242

CPC分类号： H01L21/28194 ,  H01L21/2807 ,  H01L21/28123 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/517

摘要： The present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high-K dielectric material a polysilicon or polysilicon-germanium layer; and forming a gate stack by plasma etching both a portion of the polysilicon or polysilicon-germanium layer and a portion of the layer comprising a high-K dielectric material in a single chamber. In one embodiment, the step of plasma etching is carried out without moving the first wafer from the chamber. In another embodiment an unwanted residual high-K dielectric material is removed by applying a low power plasma treatment.

摘要翻译： 本发明涉及制造半导体器件的方法，包括提供第一半导体晶片的步骤; 在第一半导体晶片上沉积包含高K电介质材料层的层; 在包括高K电介质材料的层上沉积多晶硅或多晶硅 - 锗层; 以及通过在单个室中等离子体蚀刻多晶硅或多晶硅 - 锗层的一部分和包含高K电介质材料的层的一部分来形成栅叠层。 在一个实施例中，在不从腔室移动第一晶片的情况下执行等离子体蚀刻的步骤。 在另一个实施例中，通过施加低功率等离子体处理来去除不想要的残余高K电介质材料。

公开(公告)号：US06445070B1

公开(公告)日：2002-09-03

申请号：US09772715

申请日：2001-01-29

申请人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Minh Van Ngo ,  Suzette K. Prangrle

发明人： Pin-Chin Connie Wang ,  Amit P. Marathe ,  Minh Van Ngo ,  Suzette K. Prangrle

IPC分类号： H01L2348

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. A barrier layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer reacts with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.

摘要翻译： 因此，提供了具有半导体器件的半导体衬底和形成在半导体衬底上的器件电介质层的集成电路和制造方法。 器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。 沉积阻挡层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成导体芯材料扩散到沟道介电层的障碍。 阻挡层与导体芯和沟道介电层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯与双重镶嵌集成电路中的导体芯扩散。

公开(公告)号：US06441490B1

公开(公告)日：2002-08-27

申请号：US09774849

申请日：2001-01-30

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2940

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.

摘要翻译： 提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。 在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。 通孔电介质层上的第二通道介电层具有第二通道开口。 填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。

公开(公告)号：US06420752B1

公开(公告)日：2002-07-16

申请号：US09502163

申请日：2000-02-11

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种用于最小化自动掺杂问题的半导体器件。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US06417100B1

公开(公告)日：2002-07-09

申请号：US09874558

申请日：2001-06-04

申请人： Steven C. Avanzino ,  Pin-Chin Connie Wang ,  Minh Van Ngo

发明人： Steven C. Avanzino ,  Pin-Chin Connie Wang ,  Minh Van Ngo

IPC分类号： H01L214763

CPC分类号： H01L21/76877

摘要： A method of manufacturing an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening provided therein is formed on the semiconductor substrate. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The integrated circuit is annealed in an atmosphere containing ammonia. This results in reduced hydrogen accumulation, improved bonding, and reduced electro-migration.

摘要翻译： 提供一种具有半导体器件的半导体衬底的集成电路的制造方法。 在半导体衬底上形成具有开口的器件介质层。 屏障层对通道开口进行排列。 导体芯填充阻挡层上的开口。 集成电路在含有氨的气氛中退火。 这导致减少的氢积聚，改善的结合和减少的电迁移。

公开(公告)号：US06383880B1

公开(公告)日：2002-05-07

申请号：US09679374

申请日：2000-10-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Robert A. Huertas

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/3105

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a plasma containing ammonia and nitrogen to create a clean surface region having increased nitrogen. Embodiments include treating the silicon nitride sidewall spacers with an ammonia and nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用包含氨和氮的等离子体处理氮化硅侧壁间隔物的暴露表面以产生具有增加的氮的清洁表面区域来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氨和氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06348732B1

公开(公告)日：2002-02-19

申请号：US09715702

申请日：2000-11-18

申请人： Sergey D. Lopatin ,  Minh Van Ngo ,  Minh Quoc Tran

发明人： Sergey D. Lopatin ,  Minh Van Ngo ,  Minh Quoc Tran

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 电介质层位于半导体衬底上，其中设有开口。 非晶化的阻挡层对开口进行排列，并且沉积种子层以使非晶化的阻挡层排列。 导体芯填充阻挡层上的开口以形成导体通道。 种子层牢固地结合到非晶化阻挡层并防止沿种子和阻挡层之间的表面的电迁移。

公开(公告)号：US06333218B1

公开(公告)日：2001-12-25

申请号：US09501995

申请日：2000-02-11

申请人： Minh Van Ngo ,  Jayendra Bhakta ,  Paul Besser

发明人： Minh Van Ngo ,  Jayendra Bhakta ,  Paul Besser

IPC分类号： H01L218238

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76224

摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

摘要翻译： 半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。 使用高温高密度等离子体（HDP）沉积，氧化物作为沟槽衬垫沉积在沟槽中。 由于高温HDP氧化物沉积是应力中性过程，因此避免了硅衬底和氧化物层之间的界面处的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处超范围。 当局部互连形成时，这减少了结漏电的可能性。

公开(公告)号：US06214731B1

公开(公告)日：2001-04-10

申请号：US09442771

申请日：1999-11-18

申请人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

发明人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

摘要翻译： 具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。 沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。 然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。