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101.发明授权Strained silicon on relaxed sige film with uniform misfit dislocation density 有权应变硅在轻松的超薄膜上具有均匀的失配位错密度公开(公告)号：US06872641B1
公开(公告)日：2005-03-29
申请号：US10667603
申请日：2003-09-23
IPC分类号： H01L21/205 , C30B1/00 , H01L21/20 , H01L21/265 , H01L21/322 , H01L21/324 , H01L21/36 , H01L29/10
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/1054
摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained layer. During the annealing, interstitial dislocation loops are formed as uniformly tributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.
摘要翻译： 提供一种形成半导体衬底结构的方法。 在硅衬底上形成压缩应变SiGe层。 原子被离子注入SiGe层以造成范围内的损伤。 进行退火以松弛应变层。 在退火过程中，间隙位错环形成均匀分布在SiGe层中。 间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。 由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。 在松弛的SiGe层上形成拉伸应变硅层。
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102.发明授权公开(公告)号：US06787838B1
公开(公告)日：2004-09-07
申请号：US10250259
申请日：2003-06-18
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/1203
摘要： A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.
摘要翻译： SOI晶片中的沟槽电容器DRAM单元使用阵列中的硅器件层作为通过字线的一部分，剥离字线外的阵列中的硅器件层，并使用BOX层作为阵列顶部氧化物，将通过的字线与 基质。
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公开(公告)号：US06777737B2
公开(公告)日：2004-08-17
申请号：US10016605
申请日：2001-10-30
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
摘要翻译： 具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。 具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。 每个存储单元包括覆盖沟槽电容器的垂直晶体管。 在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。 穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。
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公开(公告)号：US06653678B2
公开(公告)日：2003-11-25
申请号：US09904612
申请日：2001-07-13
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
摘要翻译： 半导体衬底中的深沟槽（DT）电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。 在轴环下形成一个外板。 电容电介质形成在轴环下面的DT壁上。 节点电极形成在DT上，凹陷在DT顶部下方。 衣领凹入DT。 在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。 可以在形成凹陷环的外围边缘之后形成盖，然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质，例如， Ge，进入节点电极和带子。 或者，节点电极凹进，随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。
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公开(公告)号：US06573585B2
公开(公告)日：2003-06-03
申请号：US09769453
申请日：2001-01-26
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
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公开(公告)号：US06534824B1
公开(公告)日：2003-03-18
申请号：US10078926
申请日：2002-02-20
IPC分类号： H01L2976
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.
摘要翻译： 6F2存储单元结构及其制造方法。 存储单元结构包括位于含Si衬底中的以行和列排列的多个存储单元。 每个存储单元包括具有暴露的栅极导体区域和形成在MOSFET的相对侧壁上的两个栅极的双门控垂直MOSFET。 存储单元结构还包括覆盖双门控垂直MOSFET并与暴露的栅极导体区域接触的多个字线以及与字线正交的多个位线。 沟槽隔离区位于与存储单元行相邻的位置。 存储单元结构还包括位于含硅衬底中并与字线和位线自对准的多个穿通停止区域。 穿通停止区域的一部分在位线之下彼此重叠，并且每个区域用于将相邻的掩埋区域彼此电隔离。
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公开(公告)号：US08492802B2
公开(公告)日：2013-07-23
申请号：US13593659
申请日：2012-08-24
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译： 电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。 此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加 取决于通道长度相对于晶体结构的对准。 给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。
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公开(公告)号：US08492268B2
公开(公告)日：2013-07-23
申请号：US13410466
申请日：2012-03-02
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。
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109.发明申请Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor 有权互补金属氧化物半导体（CMOS）器件，其栅极结构由金属栅极导体连接公开(公告)号：US20130168776A1
公开(公告)日：2013-07-04
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。
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公开(公告)号：US08453100B2
公开(公告)日：2013-05-28
申请号：US12873554
申请日：2010-09-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region. The second region and the third region share perimeters in the second direction. The method then separately evaluates effects the other transistor elements have within each of the first region, the second region, and the third region, to determine a characteristic of the gate conductor.
摘要翻译： 方法（和计算机程序）识别晶体管元件在几何电路布局内的形状和位置。 晶体管元件包括有源区，至少一个栅极导体和其它晶体管元件。 此外，栅极导体具有沿第一方向延伸的侧面，并且具有沿垂直于第一方向的第二方向延伸的宽度尺寸。 该方法定义几何电路布局内的区域。 为此，该方法限定了具有沿着栅极导体的侧面定位的周边的第一区域，其中栅极导体与有源区域相交，然后在第二方向上将第一区域的周边扩展到有源区域的边缘，以限定 第二区域的周边。 第一个区域和第二个共享周边的第一个方向。 该方法然后在第一方向上扩展第二区域的周边以限定第三区域的周长。 第二区域和第三区域在第二方向共享周边。 该方法然后分别评估其它晶体管元件在第一区域，第二区域和第三区域内的效应，以确定栅极导体的特性。
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