利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

130 条记录 (耗时 0.039 秒)

    Shift register and image display device
    102.
    发明授权
    Shift register and image display device 有权
    移位寄存器和图像显示设备

    公开(公告)号：US07212184B2

    公开(公告)日：2007-05-01

    申请号：US10800352

    申请日：2004-03-12

    申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0289

    摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.

    摘要翻译： 在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。 时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。 此外，使用两种时钟信号，每个时钟信号的占空比不大于50％，并且在其低电平时段中没有重叠部分，以便防止移位寄存器的输出与每个 其他。 因此，可以提供优选用于图像显示装置的驱动电路的移位寄存器，可以使驱动电路小型化，并且可以期望地改变输出信号的脉冲宽度，并且还提供图像显示装置 使用这种移位寄存器。

    Level shift circuit
    103.
    发明授权
    Level shift circuit 有权
    电平移位电路

    公开(公告)号：US07212059B2

    公开(公告)日：2007-05-01

    申请号：US11103893

    申请日：2005-04-12

    申请人： Yasushi Kubota ,  Masahiro Sato ,  Hiroshi Watanabe

    发明人： Yasushi Kubota ,  Masahiro Sato ,  Hiroshi Watanabe

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113 ,  H03K17/223

    摘要： The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. Level shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.

    摘要翻译： 电路是提供一种类型的电平移位电路，即使当来自多个电源的电压的输入定时不同时也能正常工作。 作为对低电压源的输入信号的响应而输出高电压源的输出信号的电平移位电路10具有以下属性：当相对于高电压源的馈送而言，低电压源的馈电被延迟时， 基于高电压源，上电复位电路20产生上电复位信号PWR。 在将低电压源的输入信号作为对上电复位PWR的响应进给之前的期间，锁存电路30初始化电平移位电路，并将其输出OUT保持在低电平。

    Signal line driving circuit and image display device
    108.
    发明申请
    Signal line driving circuit and image display device 审中-公开

    公开(公告)号：US20060181502A1

    公开(公告)日：2006-08-17

    申请号：US11402352

    申请日：2006-04-11

    申请人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Cairns ,  Michael Brownlow

    发明人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Cairns ,  Michael Brownlow

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3677 ,  G09G2310/0289

    摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

    Driving circuit of liquid crystal display device
    109.
    发明授权
    Driving circuit of liquid crystal display device 有权

    公开(公告)号：US07079121B2

    公开(公告)日：2006-07-18

    申请号：US09928988

    申请日：2001-08-15

    申请人： Jun Koyama ,  Yukio Tanaka ,  Yasushi Kubota ,  Tamotsu Sakai

    发明人： Jun Koyama ,  Yukio Tanaka ,  Yasushi Kubota ,  Tamotsu Sakai

    IPC分类号： G09G3/36

    CPC分类号： H01L27/124 ,  G02F1/1362 ,  G02F2001/13629 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2320/0209 ,  G09G2320/0223

    摘要： A driving circuit of a liquid crystal display device including a first insulating substrate on which a plurality of signal lines and a plurality of scan lines are disposed, and pixel transistors made of thin film transistors are disposed in matrix at intersection points of those lines; a second insulating substrate opposite to the first insulating substrate; and a liquid crystal held between the first and second insulating substrates, in which the driving circuit is disposed on the first insulating substrate; each of clock lines or base portions of the clock lines for supplying clock signals to the driving circuit is made of a two-layer structure of the same wiring material as a gate electrode of the thin film transistor and the same wiring material as a source electrode or drain electrode of the thin film transistor; and a wiring line crossing the clock lines or the base portions of the clock lines is made of a wiring line in the same layer as a black matrix covering the pixel transistors.

    Matrix image display device
    110.
    发明授权
    Matrix image display device 失效

    公开(公告)号：US07034795B2

    公开(公告)日：2006-04-25

    申请号：US10208757

    申请日：2002-08-01

    申请人： Kazuhiro Maeda ,  Hajime Washio ,  Yasushi Kubota

    发明人： Kazuhiro Maeda ,  Hajime Washio ,  Yasushi Kubota

    IPC分类号： G06G3/36

    CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G2310/021 ,  G09G2310/0251 ,  G09G2320/0209 ,  G09G2340/0414

    摘要： The scanning signal line driving circuit sequentially carries out active driving with respect to each set of a certain number of scanning signal lines which are adjacent to each other in a vertical direction, and when carrying out an actual writing with respect to a first set of a certain number of pixel lines adjacent to each other in the vertical direction, carries out pre-charging with respect to a second set of the certain number of pixel lines to which the actual writing is carried out next with a potential of a same polarity as that of the first set of the certain number of pixel lines. In this manner, it is possible to provide a matrix image display device with no irregularities in display quality and is capable of matching the apparent vertical resolution of the device to that of the image source, when using an image signal of vertical resolution lower than the maximum physical vertical resolution of the device.