公开(公告)号：US20230133023A1

公开(公告)日：2023-05-04

申请号：US17513273

申请日：2021-10-28

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.

公开(公告)号：US11502242B2

公开(公告)日：2022-11-15

申请号：US16828489

申请日：2020-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L43/12 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32

Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.

公开(公告)号：US11495538B2

公开(公告)日：2022-11-08

申请号：US16932731

申请日：2020-07-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Chih-Chao Yang ,  Lawrence A. Clevenger ,  Ashim Dutta

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A fully aligned via interconnect structure and techniques for formation thereof using subtractive metal patterning are provided. In one aspect, an interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; and at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx, wherein a top surface of at least one of the metal lines Mx−1 has a stepped profile. In another aspect, another interconnect structure includes: metal lines Mx−1; metal lines Mx disposed over the metal lines Mx−1; at least one via Vx−1 fully aligned between the metal lines Mx−1 and the metal lines Mx; and sidewall spacers alongside the metal lines Mx. A method of forming an interconnect structure is also provided.

公开(公告)号：US20220285606A1

公开(公告)日：2022-09-08

申请号：US17249521

申请日：2021-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Yann Mignot ,  Ashim Dutta ,  Tsung-Sheng Kang ,  Wenyu Xu

IPC: H01L43/02 ,  H01L43/12

Abstract: A semiconductor structure may include a magnetic tunnel junction layer on top and in electrical contact with a microstud, a hard mask layer on top of the magnetic tunnel junction layer, and a liner positioned along vertical sidewalls of the magnetic tunnel junction layer and vertical sidewalls of the hard mask layer. A top surface of the liner may be below a top surface of the hard mask layer. The semiconductor structure may include a spacer on top of the liner. The liner may separate the spacer from the magnetic tunnel junction layer and the hard mask layer. The semiconductor structure may include a first metal layer below and in electrical contact with the microstud and a second metal layer above the hard mask layer. A bottom portion of the second metal layer may surround a top portion of the hard mask layer.

公开(公告)号：US11373880B2

公开(公告)日：2022-06-28

申请号：US17028317

申请日：2020-09-22

Applicant: International Business Machines Corporation

Inventor： Christopher J Penny ,  Ekmini Anuja De Silva ,  Ashim Dutta ,  Abraham Arceo de la Pena

IPC: H01L21/3213 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311

Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.

公开(公告)号：US20220109099A1

公开(公告)日：2022-04-07

申请号：US17552027

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Rizzolo ,  Theodorus E. Standaert ,  Ashim Dutta ,  Dominik Metzler

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L45/00 ,  H01L43/12 ,  H01L27/24 ,  H01L43/08

Abstract: A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.

公开(公告)号：US20220093414A1

公开(公告)日：2022-03-24

申请号：US17028317

申请日：2020-09-22

Applicant: International Business Machines Corporation

Inventor： Christopher J Penny ,  Ekmini Anuja De Silva ,  Ashim Dutta ,  Abraham Arceo de la Pena

IPC: H01L21/3213 ,  H01L23/528 ,  H01L21/311 ,  H01L21/033

Abstract: An approach provides a semiconductor structure with a semiconductor layer that has a plurality of metal lines on the semiconductor layer where a first line of the plurality of metal lines on the semiconductor layer has a different line width than a second line of the plurality of metal lines on the semiconductor layer and a low-k dielectric material covers the plurality of metal lines and the semiconductor layer between the plurality of metal lines.

公开(公告)号：US20210398816A1

公开(公告)日：2021-12-23

申请号：US17467428

申请日：2021-09-06

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

IPC: H01L21/308 ,  H01L21/033

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

公开(公告)号：US20210375986A1

公开(公告)日：2021-12-02

申请号：US16886830

申请日：2020-05-29

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

公开(公告)号：US20210358801A1

公开(公告)日：2021-11-18

申请号：US16874658

申请日：2020-05-14

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saumya Sharma ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for making a semiconductor apparatus includes forming a first bottom interconnect in a device area of a first dielectric layer; fabricating a device on top of the first bottom interconnect; capping the device with a first interlayer dielectric; exposing a logic area of the first dielectric layer that is adjacent to the device area by removing a portion of the first interlayer dielectric from the first dielectric layer while leaving another portion of the first interlayer dielectric that caps the device; and forming a second bottom interconnect in the logic area of the first dielectric layer. By forming the second bottom interconnect after the device fabrication and capping, damage to the device and to the second bottom interconnect is avoided.