公开(公告)号：US11526796B2

公开(公告)日：2022-12-13

申请号：US16929922

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer

IPC: G06N10/00 ,  G06N10/20 ,  G06F11/34 ,  G06F11/30 ,  B82Y10/00 ,  H03K19/195

Abstract: Systems and techniques that facilitate qubit pulse calibration via canary parameter monitoring are provided. In various embodiments, a system can comprise a measurement component that can measure a canary parameter associated with a qubit control channel. In various embodiments, the system can further comprise a scaling component that can modify a plurality of parameters associated with the qubit control channel via a scaling factor. In various cases, the scaling factor can be based on the canary parameter. In various embodiments, the canary parameter can be a rotation error of a qubit driven by a microwave pulse transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be amplitudes of a plurality of microwave pulses transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be phases of a plurality of microwave pulses transmitted along the qubit control channel.

公开(公告)号：US20220093772A1

公开(公告)日：2022-03-24

申请号：US17542566

申请日：2021-12-06

Applicant: International Business Machines Corporation

Inventor： Josephine Chang ,  Isaac Lauer ,  Jeffrey Sleight

IPC: H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L21/768 ,  H01L29/786 ,  H01L51/05

Abstract: A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

公开(公告)号：US20220028927A1

公开(公告)日：2022-01-27

申请号：US16935698

申请日：2020-07-22

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Neereja Sundaresan

IPC: H01L27/18 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles. In various embodiments, the qubit lattice can exhibit a rectilinear physical layout. In various embodiments, the one or more first qubit tiles tessellated with the one or more second qubit tiles can form a heavy-hex qubit connection topology in the rectilinear physical layout of the qubit lattice. In various embodiments, one of the one or more first qubit tiles can have twelve qubits and twelve interqubit connection buses. In various cases, one of the one or more second qubit tiles can have twelve qubits and twelve interqubit connection buses. In various embodiments, adjacent qubit tiles in the heavy-hex qubit connection topology can share three qubits. In various embodiments, a qubit tile in the heavy-hex qubit connection topology can be adjacent to four qubit tiles having a different shape than the qubit tile. In various cases, the qubit tile can be adjacent to two qubit tiles having a same shape as the qubit tile.

公开(公告)号：US20210342161A1

公开(公告)日：2021-11-04

申请号：US16861653

申请日：2020-04-29

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Oliver Dial ,  Matthias Steffen

IPC: G06F9/4401 ,  G06N10/00 ,  H04B10/70

Abstract: Techniques regarding resetting highly excited qubits are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a reset component that can de-excite a qubit system to a target state by transitioning a population of a first excited state of the qubit system to a ground state and by applying a signal to the qubit system that transitions a population of a second excited state to the first excited state.

公开(公告)号：US20210258079A1

公开(公告)日：2021-08-19

申请号：US16795149

申请日：2020-02-19

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Neereja Sundaresan

IPC: H04B10/90 ,  G06N10/00

Abstract: Systems, computer-implemented methods, and/or computer program products that can facilitate target qubit decoupling in an echoed cross-resonance gate are provided. According to an embodiment, a computer-implemented method can comprise receiving, by a system operatively coupled to a processor, both a cross-resonance pulse and a decoupling pulse at a target qubit. The cross-resonance pulse propagates to the target qubit via a control qubit. The computer-implemented method can further comprise receiving, by the system, a state inversion pulse at the control qubit. The computer-implemented method can further comprise receiving, by the system, both a phase-inverted cross-resonance pulse and a phase-inverted decoupling pulse at the target qubit. The phase-inverted cross-resonance pulse propagates to the target qubit via the control qubit.

公开(公告)号：US11004678B2

公开(公告)日：2021-05-11

申请号：US16667987

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US10522342B2

公开(公告)日：2019-12-31

申请号：US16002561

申请日：2018-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US10367062B2

公开(公告)日：2019-07-30

申请号：US15986079

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.

公开(公告)号：US10361304B2

公开(公告)日：2019-07-23

申请号：US16011124

申请日：2018-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Isaac Lauer ,  Jiaxing Liu ,  Renee T. Mo

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/324 ,  H01L21/306 ,  H01L21/84

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

公开(公告)号：US20180277626A1

公开(公告)日：2018-09-27

申请号：US15986079

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L29/06 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/306 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.