公开(公告)号：US09183063B2

公开(公告)日：2015-11-10

申请号：US13680295

申请日：2012-11-19

Applicant: International Business Machines Corporation

Inventor： Hans M. Jacobson ,  Ravi Nair ,  John K. P. O'Brien ,  Zehra N. Sura

IPC: G06F9/50 ,  G06F9/46 ,  G06F1/32 ,  G06F9/48 ,  G06F9/45

CPC classification number: G06F9/5094 ,  G06F1/329 ,  G06F8/41 ,  G06F9/46 ,  G06F9/4893 ,  Y02D10/24

Abstract: An active memory system includes a computer and an active memory device including layers of memory forming a three-dimensional memory device and individual columns of chips forming vaults in communication with a processing element and logic. The processing element is configured to communicate to the chips and other processing elements. The active memory system also includes a compiler configured to implement a method. The method includes dividing a power budget for the active memory device into a discrete number of power tokens, each of the power tokens having an equal value of units of power. The method also includes determining a power requirement for executing a code segment on the processing element of the active memory device based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, one or more power tokens to satisfy the power requirement.

Abstract translation: 有源存储器系统包括计算机和主动存储器件，其包括形成三维存储器件的存储器层和形成与处理元件和逻辑通信的保险库的各个芯片列。 处理元件被配置为与芯片和其它处理元件通信。 活动存储器系统还包括被配置为实现方法的编译器。 该方法包括将有源存储器件的功率预算分成离散数量的功率标记，每个功率令牌具有相等的功率单位值。 该方法还包括基于处理元件和代码段的特性来确定在有源存储器件的处理元件上执行代码段的功率需求。 该方法还包括在运行时向处理元件分配一个或多个功率令牌以满足功率需求。

公开(公告)号：US09104465B2

公开(公告)日：2015-08-11

申请号：US13684657

申请日：2012-11-26

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/46 ,  G06F9/3877 ,  G06F9/5044 ,  G06F2209/509 ,  Y02D10/22

Abstract: According to one embodiment of the present invention, a computer system for executing a task includes a main processor, a processing element and memory. The computer system is configured to perform a method including receiving, at the processing element, the task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request including execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.

Abstract translation: 根据本发明的一个实施例，用于执行任务的计算机系统包括主处理器，处理元件和存储器。 计算机系统被配置为执行一种方法，包括在处理元件处接收来自主处理器的任务，由处理元件执行由该任务指定的指令，由处理元件确定功能是 在所述主处理器上执行所述功能是所述任务的一部分，由所述处理元件向所述主处理器发送请求以执行所述请求，所述请求包括所述功能的执行，并且在所述处理元件处接收所述处理元件的指示， 主处理器已完成执行请求指定的功能。

公开(公告)号：US09104464B2

公开(公告)日：2015-08-11

申请号：US13669877

申请日：2012-11-06

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/46 ,  G06F9/3877 ,  G06F9/5044 ,  G06F2209/509 ,  Y02D10/22

Abstract: According to one embodiment of the present invention, a method for operating a computer system including a main processor, a processing element and memory is provided. The method includes receiving, at the processing element, a task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request comprising execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.

Abstract translation: 根据本发明的一个实施例，提供了一种用于操作包括主处理器，处理元件和存储器的计算机系统的方法。 该方法包括在处理单元处接收来自主处理器的任务，由处理单元执行由任务指定的指令，由处理单元确定要在主处理器上执行功能， 所述功能是所述任务的一部分，由所述处理元件发送对所述主处理器执行的请求，所述请求包括所述功能的执行，并且在所述处理元件处接收到所述主处理器已完成所述主处理器的执行的指示 函数由请求指定。

公开(公告)号：US20140195744A1

公开(公告)日：2014-07-10

申请号：US13761252

申请日：2013-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request.

Abstract translation: 根据一个实施例，提供了一种存储器件。 存储器件包括耦合到交叉开关互连的处理元件。 处理元件被配置为向交叉开关互连发送包括优先级值的存储器访问请求。 交叉开关互连被配置为将存储器访问请求路由到与存储器访问请求相关联的存储器控​​制器。 存储器控制器耦合到存储器和交叉开关互连。 存储器控制器包括队列，并被配置为将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求并执行下一个存储器 基于最高优先级存储器访问请求的访问请求。