中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

49 records (took 0.021 seconds)

    Power management for a computer system
    3.
    发明授权
    Power management for a computer system 有权
    计算机系统的电源管理

    公开(公告)号：US09201490B2

    公开(公告)日：2015-12-01

    申请号：US13837655

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Pradip Bose ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/48 ,  G06F9/44

    CPC classification number: G06F1/3243 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3278 ,  G06F3/0656 ,  G06F9/3877 ,  G06F9/44 ,  G06F9/4893 ,  G06F13/00 ,  G06F13/1663 ,  G06F2212/312 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

    Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

    Abstract translation: 实施例包括一种用于管理计算机系统中的电力的方法，所述计算机系统包括主处理器和包括供电单元的主动存储器设备，所述主存储器设备通过存储器链路与所述主处理器通信，所述动力单元包括处理元件。 该方法包括主处理器在程序线程上执行程序，遇到要由有源存储器件执行的代码的第一部分，通过第一命令改变有源存储器件上的供电单元的功率状态，基于 主处理器遇到第一部分代码，第一个命令包括一个存储命令。 该方法还包括处理元件在第二时间执行代码的第一部分，基于执行第一部分的处理元件，将主处理器的功率状态从功率使用状态改变到省电状态。

    Sequential location accesses in an active memory device
    4.
    发明授权
    Sequential location accesses in an active memory device 有权
    有源存储设备中的顺序位置访问

    公开(公告)号：US09104532B2

    公开(公告)日：2015-08-11

    申请号：US13714724

    申请日：2012-12-14

    Applicant: International Business Machines Corporation

    Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F12/00 ,  G06F17/30 ,  G06F7/00

    CPC classification number: G06F12/00 ,  G06F9/3877 ,  G06F11/00 ,  G06F13/00 ,  G06F15/785

    Abstract: Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values.

    Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器设备中的顺序位置访问。 一个方面包括用于顺序位置访问的方法，其包括从存储器接收与处理元件上的队列条目相关联的第一组数据值。 读取与队列条目相关联并且指定提取数据值的第一子集的位置的标签值。 队列条目用从标签值指定的位置开始的数据值的第一个子集填充。 处理元件确定第一组数据值中的数据值的第二子集是否与后续的队列条目相关联，并且用数据值的第二子集填充后续队列条目的一部分。

    POWER MANAGEMENT FOR IN-MEMORY COMPUTER SYSTEMS
    5.
    发明申请
    POWER MANAGEMENT FOR IN-MEMORY COMPUTER SYSTEMS 有权
    内存计算机系统的电源管理

    公开(公告)号：US20150177811A1

    公开(公告)日：2015-06-25

    申请号：US14133861

    申请日：2013-12-19

    Applicant: International Business Machines Corporation

    Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Augusto J. Vega

    IPC: G06F1/32

    CPC classification number: G06F1/329 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

    Abstract: According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the power cap, actions are performed including: reducing power provided to a first power-consuming component based on determining that it has an activity level below a first threshold and that power can be reduced to the first power-consuming component. Power provided to a second power-consuming component is reduced based on determining that it has an activity level below a second threshold and that power can be reduced to the second power-consuming component. Power reduction is forced in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component.

    Abstract translation: 根据一个实施例，提供了一种用于包括至少两个功耗组件的计算节点的功率管理的方法。 功率上限控制系统将计算节点的功耗级别与功率上限进行比较。 基于确定功耗水平大于功率上限，执行动作，包括：基于确定其具有低于第一阈值的活动水平并且该功率可以减小到第一功耗组件来提供的功率 第一个耗电量的组件。 基于确定其具有低于第二阈值的活动水平并且该功率可以减小到第二功耗组件，提供给第二功耗组件的功率被减小。 基于确定在第一或第二功耗组件中的任何一个中不能降低功率，在计算节点中强制降低功率。

    Exposed-pipeline processing element with rollback
    6.
    发明授权
    Exposed-pipeline processing element with rollback 有权
    具有回滚的暴露流水线处理元素

    公开(公告)号：US08990620B2

    公开(公告)日：2015-03-24

    申请号：US13677746

    申请日：2012-11-15

    Applicant: International Business Machines Corporation

    Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F11/14

    CPC classification number: G06F11/14 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F11/1405 ,  G06F12/10 ,  Y02D10/13

    Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

    Abstract translation: 一个方面包括在暴露流水线处理元件中提供回滚支持。 系统包括具有回滚支持逻辑的暴露流水线处理元件。 回滚支持逻辑被配置为检测与暴露流水线处理元件中的指令的执行相关联的错误。 回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。 基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。

    MAIN PROCESSOR SUPPORT OF TASKS PERFORMED IN MEMORY
    7.
    发明申请
    MAIN PROCESSOR SUPPORT OF TASKS PERFORMED IN MEMORY 有权
    主要处理器支持在记忆体中执行的任务

    公开(公告)号：US20140130051A1

    公开(公告)日：2014-05-08

    申请号：US13684657

    申请日：2012-11-26

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F9/46

    CPC classification number: G06F9/46 ,  G06F9/3877 ,  G06F9/5044 ,  G06F2209/509 ,  Y02D10/22

    Abstract: According to one embodiment of the present invention, a computer system for executing a task includes a main processor, a processing element and memory. The computer system is configured to perform a method including receiving, at the processing element, the task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request including execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.

    Abstract translation: 根据本发明的一个实施例，用于执行任务的计算机系统包括主处理器，处理元件和存储器。 计算机系统被配置为执行一种方法，包括在处理元件处接收来自主处理器的任务，由处理元件执行由该任务指定的指令，由处理元件确定功能是 在所述主处理器上执行所述功能是所述任务的一部分，由所述处理元件向所述主处理器发送请求以执行所述请求，所述请求包括所述功能的执行，并且在所述处理元件处接收所述处理元件的指示， 主处理器已完成执行请求指定的功能。

    On-chip traffic prioritization in memory
    10.
    发明授权
    On-chip traffic prioritization in memory 有权
    内存中的片上流量优先级

    公开(公告)号：US09405712B2

    公开(公告)日：2016-08-02

    申请号：US13761252

    申请日：2013-02-07

    Applicant: International Business Machines Corporation

    Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

    IPC: G06F12/00 ,  G06F13/18 ,  G06F9/48 ,  G06F13/16

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

    Abstract: According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request.

    Abstract translation: 根据一个实施例，提供了一种存储器件。 存储器件包括耦合到交叉开关互连的处理元件。 处理元件被配置为向交叉开关互连发送包括优先级值的存储器访问请求。 交叉开关互连被配置为将存储器访问请求路由到与存储器访问请求相关联的存储器控​​制器。 存储器控制器耦合到存储器和交叉开关互连。 存储器控制器包括队列，并被配置为将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求并执行下一个存储器 基于最高优先级存储器访问请求的访问请求。

Patent Agency Ranking