公开(公告)号：US12094525B2

公开(公告)日：2024-09-17

申请号：US17814254

申请日：2022-07-22

Applicant: International Business Machines Corporation

Inventor： Ravi Nair ,  Swagath Venkataramani ,  Vijayalakshmi Srinivasan ,  Arvind Kumar

IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C5/06 ,  G11C11/4093

Abstract: A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

公开(公告)号：US20210216858A1

公开(公告)日：2021-07-15

申请号：US16739694

申请日：2020-01-10

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Ravi Nair

IPC: G06N3/08 ,  G06N3/10

Abstract: Training machine learning systems using a training data set, gradient descent, and a loss function. The machine learning system includes memory and reads and writes to memory according to read and write profiles. The loss function is associated with machine learning system memory read and write profile gradients. The loss function includes a loss function penalty term, the loss function penalty term being associated with the read and write profile gradient differences. Trained machine learning systems are then provided.

公开(公告)号：US10572263B2

公开(公告)日：2020-02-25

申请号：US15086947

申请日：2016-03-31

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas Winters Fox ,  Arpith C. Jacob ,  Hans Mikael Jacobson ,  Ravi Nair ,  Kevin John Patrick O'Brien ,  Daniel Arthur Prener

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.

公开(公告)号：US10120810B2

公开(公告)日：2018-11-06

申请号：US15829032

申请日：2017-12-01

Applicant: International Business Machines Corporation

Inventor： Philip Heidelberger ,  Hillery C. Hunter ,  James A. Kahle ,  Ravi Nair

IPC: G06F12/12 ,  G06F12/0888 ,  G06F12/126

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

公开(公告)号：US10007242B2

公开(公告)日：2018-06-26

申请号：US14736758

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Bryan S. Rosenburg

IPC: G05B15/02

CPC classification number: G05B15/02

Abstract: A computer detects a request by a process for access to a shadow control page, wherein the shadow control page allows the process access to one or more devices. The computer assigns the shadow control page and a key to the process associated with the request. The computer detects a request by the process via the assigned shadow control page for creation of a subset of devices from the one or more devices. The computer inputs information detailing an association between the subset of devices and the assigned key into a subset definition table, wherein the subset definition table includes one or more keys and one or more corresponding subsets.

公开(公告)号：US09841926B2

公开(公告)日：2017-12-12

申请号：US15198868

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/18 ,  G06F13/16 ,  G06F9/48

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

公开(公告)号：US09594558B2

公开(公告)日：2017-03-14

申请号：US15245946

申请日：2016-08-24

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Chen-Yong Cher ,  Ravi Nair

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3863 ,  G06F11/00 ,  G06F11/30

Abstract: An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

Abstract translation: 一方面包括接收包括存储器地址和写数据的写请求。 从存储器地址的存储器位置读取存储的数据。 基于确定存储器位置未被修改，将存储的数据与写入数据进行比较。 基于与写入数据匹配的存储数据，完成写入请求而不将写入数据写入存储器，并且设置无声存储位图中的相应静默存储位。 基于与写入数据不匹配的存储数据，将写入数据写入存储器位置，无声存储位被复位并且相应的修改位被置位。 为应用程序和操作系统中的至少一个提供对静默存储位图的访问。

公开(公告)号：US09389675B2

公开(公告)日：2016-07-12

申请号：US14133861

申请日：2013-12-19

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Augusto J. Vega

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24

Abstract: According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the power cap, actions are performed including: reducing power provided to a first power-consuming component based on determining that it has an activity level below a first threshold and that power can be reduced to the first power-consuming component. Power provided to a second power-consuming component is reduced based on determining that it has an activity level below a second threshold and that power can be reduced to the second power-consuming component. Power reduction is forced in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component.

Abstract translation: 根据一个实施例，提供了一种用于包括至少两个功耗组件的计算节点的功率管理的方法。 功率上限控制系统将计算节点的功耗级别与功率上限进行比较。 基于确定功耗水平大于功率上限，执行动作，包括：基于确定其具有低于第一阈值的活动水平并且该功率可以减小到第一功耗组件来提供的功率 第一个耗电量的组件。 基于确定其具有低于第二阈值的活动水平并且该功率可以减小到第二功耗组件，提供给第二功耗组件的功率被减小。 基于确定在第一或第二功耗组件中的任何一个中不能降低功率，在计算节点中强制降低功率。

公开(公告)号：US09064030B2

公开(公告)日：2015-06-23

申请号：US13688530

申请日：2012-11-29

Applicant: International Business Machines Corporation

Inventor： James A. Kahle ,  Jaime H. Moreno ,  Ravi Nair

IPC: G06F17/30

CPC classification number: G06F17/30961 ,  G06F17/30327 ,  G06F17/30362

Abstract: Embodiments relate to tree traversal in a memory device. An aspect includes a method for tree traversal in a memory device. The method includes receiving a pointer to a tree structure within memory of the memory device. An evaluation condition is received to identify a desired node of the tree structure. The tree structure is traversed to identify the desired node. Data is returned from the desired node meeting the evaluation condition.

Abstract translation: 实施例涉及存储器设备中的树遍历。 一方面包括用于在存储器设备中进行树遍历的方法。 该方法包括在存储器件的存储器内接收指向树结构的指针。 接收评估条件以识别树结构的所需节点。 遍历树结构以识别所需的节点。 数据从满足评估条件的所需节点返回。

公开(公告)号：US08972782B2

公开(公告)日：2015-03-03

申请号：US13673221

申请日：2012-11-09

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Daniel A. Prener

IPC: G06F11/14

CPC classification number: G06F11/14 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F11/1405 ,  G06F12/10 ,  Y02D10/13

Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

Abstract translation: 一个方面包括在暴露流水线处理元件中提供回滚支持。 用于在暴露流水线处理元件中提供回滚支持的方法包括通过回滚支持逻辑来检测与暴露流水线处理元件中的指令的执行相关联的错误。 回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。 基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。