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    Death domain containing receptor 4 antibody and methods
    101.
    发明授权
    Death domain containing receptor 4 antibody and methods 有权
    含有受体4抗体的死亡域和方法

    公开(公告)号：US07476384B2

    公开(公告)日：2009-01-13

    申请号：US11076187

    申请日：2005-03-10

    Applicant: Jian Ni ,  Craig A. Rosen ,  James Pan ,  Reiner L. Gentz ,  Vishva M. Dixit

    Inventor： Jian Ni ,  Craig A. Rosen ,  James Pan ,  Reiner L. Gentz ,  Vishva M. Dixit

    IPC: A61K39/395 ,  A61K38/21 ,  C07K14/56 ,  C07K14/705

    CPC classification number: C07K14/70578

    Abstract: The present invention relates to novel Death Domain Containing Receptor-4 (DR4) proteins which are members of the tumor necrosis factor (TNF) receptor family. In particular, isolated nucleic acid molecules are provided encoding the human DR4 proteins. DR4 polypeptides are also provided as are vectors, host cells and recombinant methods for producing the same. The invention further relates to screening methods for identifying agonists and antagonists of DR4 activity and methods for using DR4 polynucleotides and polypeptides. The invention also relates to the treatment of diseases associated with reduced or increased levels of apoptosis using antibodies specific for DR4, which may be agonists and/or antagonists of DR4 activity.

    Abstract translation: 本发明涉及作为肿瘤坏死因子（TNF）受体家族成员的新的含有死亡域的受体-4（DR4）蛋白。 特别地，提供编码人DR4蛋白的分离的核酸分子。 还提供了DR4多肽，载体，宿主细胞和用于制备它们的重组方法。 本发明还涉及用于鉴定DR4活性的激动剂和拮抗剂的筛选方法以及使用DR4多核苷酸和多肽的方法。 本发明还涉及使用DR4特异性抗体（其可以是DR4活性的激动剂和/或拮抗剂）的减少或增加的细胞凋亡相关疾病的治疗。

    METHODS FOR FABRICATING AN INTEGRATED CIRCUIT
    102.
    发明申请
    METHODS FOR FABRICATING AN INTEGRATED CIRCUIT 有权
    制造集成电路的方法

    公开(公告)号：US20080160688A1

    公开(公告)日：2008-07-03

    申请号：US11616858

    申请日：2006-12-28

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L21/8242

    CPC classification number: H01L21/76897 ,  H01L21/28568 ,  H01L21/288 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

    Abstract: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

    Abstract translation: 提供了用于在制造包括逻辑和存储器的IC中减小与位线的触点的纵横比的方法。 该方法包括以下步骤：形成将由金属的第一级接触的第一组器件区域和与第二级金属接触的第二组存储器位线，该第一级与第二级与第二级分开 至少一层介电材料。 导电材料通过化学镀在器件区域和位线上进行电镀，并且第一和第二导电插塞形成在导电材料上。 第一导电插头与第一级金属接触，第二导电插头与第二级金属接触。 镀覆的导电材料的厚度提供了一种自对准的方法，用于减小导电插头的纵横比。

    METAL ALLOY LAYER OVER CONDUCTIVE REGION OF TRANSISTOR DEVICE OF DIFFERENT CONDUCTIVE MATERIAL THAN CONDUCTIVE REGION
    103.
    发明申请
    METAL ALLOY LAYER OVER CONDUCTIVE REGION OF TRANSISTOR DEVICE OF DIFFERENT CONDUCTIVE MATERIAL THAN CONDUCTIVE REGION 审中-公开
    不同导电材料与导电区域的晶体管器件导电区域的金属合金层

    公开(公告)号：US20070284654A1

    公开(公告)日：2007-12-13

    申请号：US11422965

    申请日：2006-06-08

    Applicant: Judith M. Rubino ,  James Pan ,  Dinkar Singh ,  Jonathan Smith ,  Anna Topol

    Inventor： Judith M. Rubino ,  James Pan ,  Dinkar Singh ,  Jonathan Smith ,  Anna Topol

    IPC: H01L29/76

    CPC classification number: H01L29/78 ,  H01L29/7845

    Abstract: A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy layer disposed on substantially all of a surface of the conductive region, the metal alloy layer including a second conductive material different than the at least one first conductive materials. In one embodiment, the second conductive material includes a cobalt and/or nickel alloy. The metal alloy layer provides a non-epitaxial raised source/drain (and gate) to reduce the parasitic series resistance in, for example, nFETs fabricated on UTSOI. In addition, the metal alloy layer may include a stress to enhance mobility in a channel of the transistor device. The metal alloy layer may be formed using a selective electrochemical metal deposition process such as electroless or electrolytic plating.

    Abstract translation: 公开了一种晶体管器件和方法，用于在导电区域上使用金属合金层降低寄生电阻并增强沟道迁移率。 晶体管器件可以包括导电区域，例如包括至少一个第一导电材料的源极，漏极和/或栅极以及设置在导电区域的基本上所有表面上的金属合金层，金属合金层包括第二导电区域 导电材料不同于至少一种第一导电材料。 在一个实施例中，第二导电材料包括钴和/或镍合金。 金属合金层提供非外延凸起的源极/漏极（和栅极），以减少例如在UTSOI上制造的nFET的寄生串联电阻。 此外，金属合金层可以包括提高晶体管器件的沟道中的迁移率的应力。 可以使用诸如无电镀或电解电镀的选择性电化学金属沉积工艺来形成金属合金层。

    Multi-channel transistor with tunable hot carrier effect
    104.
    发明授权
    Multi-channel transistor with tunable hot carrier effect 有权
    具有可调热载流子效应的多通道晶体管

    公开(公告)号：US07224007B1

    公开(公告)日：2007-05-29

    申请号：US10873240

    申请日：2004-06-23

    Applicant: James Pan ,  Andrew M. Waite

    Inventor： James Pan ,  Andrew M. Waite

    IPC: H01L29/768

    CPC classification number: H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A multiple channel transistor provides a transistor with an improved drive current and speed by using tunable hot carrier effects. A thin gate oxide has a carrier confinement layer formed on top thereof. Holes produced by hot carrier effects are retained by the carrier confinement layer directly above the gate oxide layer. The holes switch on the bottom transistor of the multi-channel transistor, thereby increasing the drive current.

    Abstract translation: 多通道晶体管通过使用可调热载流子效应为晶体管提供了改进的驱动电流和速度。 薄栅氧化物在其顶部形成有载流子限制层。 由热载体效应产生的孔由栅极氧化物层正上方的载流子限制层保留。 空穴打开多通道晶体管的底部晶体管，从而增加驱动电流。

    Nucleic acids encoding a tumor necrosis factor homolog
    105.
    发明授权
    Nucleic acids encoding a tumor necrosis factor homolog 有权
    编码肿瘤坏死因子同源物的核酸

    公开(公告)号：US07198913B2

    公开(公告)日：2007-04-03

    申请号：US10243157

    申请日：2002-09-12

    Applicant: Audrey Goddard ,  James Pan ,  Minhong Yan

    Inventor： Audrey Goddard ,  James Pan ,  Minhong Yan

    IPC: C12P21/02 ,  C07H21/04

    CPC classification number: C12N15/10 ,  A61K38/00 ,  C07K14/4703 ,  C07K14/4705 ,  C07K14/70578 ,  C12N2799/026 ,  C12Q1/686 ,  C12Q2531/113 ,  C12Q2521/331

    Abstract: The present invention is directed to novel polypeptides having homology to members of the tumor necrosis factor receptor family and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

    Abstract translation: 本发明涉及与肿瘤坏死因子受体家族的成员具有同源性的新型多肽和编码那些多肽的核酸分子。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法 发明。

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